The Rambus Revolution Will Boost CSP Use (but Still No Free Lunch)

By Ron Iscoff Editor

A small Mountain View, Calif.-based technology company, founded by two engineering PhDs in 1990, has become one of the hottest properties in the semiconductor industry. I'm referring, of course, to Rambus Inc. Rambus has developed and licensed a family of high-performance interfaces for memory ICs. The interfaces enable semiconductor memory to keep pace with next generation CPUs and controllers.

The technology is being incorporated into DRAMS and the logic devices that control them. Rambus claims this means a 10x performance increase over conventional DRAMs. A single Rambus DRAM (known as an RDRAM) transfers data at up to 800 MHz over a two byte-wide Rambus channel to Rambus-compatible ICs.

The RDRAM will have a substantial and dramatic impact on the growth of CSPs where memory devices are concerned. Of course, most new and enabling technologies are not without their tradeoffs—but we'll get to that later.

"DRAM volumes are huge compared to other device markets," notes Nader Gamini, manager of advanced packaging technology at Rambus. Gamini describes the Rambus interface (photo) as, "a sliver of silicon that's placed on the DRAM die, either along the lower edge on in the center of the die, and contains the Rambus interface circuitry." Each chip maker employs its own method of Rambus placement and manufacture, based on a reference standard supplied by Rambus.

Today, enabled by Rambus, larger die are finding their way into CSPs, Rambus' Gamini says. The company has developed a reference standard in conjunction with Tessera and some of the major pack-aging foundries, including Amkor and ChipPAC. "We have completed a great deal of thermal, electrical and mechanical modeling," Gamini adds.

Rambus Interface Memory Module

Of course, Rambus isn't the only chip "enhancer." There have been several proposed, including one called double data rate (DDR). However, Rambus has achieved early acceptance. Not only that, the Rambus interface has been blessed by Intel. The Tessera µBGA package is the first to carry the Rambus interface, but it's likely that a number of others, including NEC's D2BGA and some flip-chip CSPs will also get the Rambus interface, Gamini said.

While Rambus has stirred great interest, it's also stirring controversy in the memory supplier community, according to Paul Sakamoto of Credence Systems, Fremont, Calif.

Sakamoto said memory suppliers will have to spend an estimated $500 million over the next two years for Rambus retooling. Most of the retooling, he added, will be in the test area, where 100 MHz-200 MHz test equipment has been adequate for the last several years.

To save this expense, it is likely that memory suppliers will avoid ATE that is capable of testing all Rambus characteristics in one socketing.

The expense of a single-socket Rambus tester is not in the timing generation or the pattern generator, Sakamoto adds. Modern high-speed CMOS-based ASIC and custom design technology have dramatically lowered these cost elements. "The current expense has shifted to the cost of the high-speed analog driver and comparator in the pin electronics," according to the Credence Systems vice president.

In general, he adds, the Rambus situation has vendors testing different parts of the device on different, specialized testers. Expect this trend to continue, Sakamoto emphasizes.

To contribute to Technology Watch, please contact the Editor at chipreview@aol.com. Announced Rambus-based System Products

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