An Expert. Paul Sakamoto on Test

An Expert Looks at the Issues

The major test issues that occur from the deployment of chip-scale packaging in memory test are the potential increase in device pin count, handler retooling and the increased performance available from this type of packaging. A secondary issue is that CSPs are enabling the development of hybrid designs that include a logic device along with one or more discrete memories. The latter brings up the possible need for either mixed technology test requirements or mixed mode testing of logic and memory functions. In all cases, a push to more socketing or a large retooling effort can be required.

What is the automatic test equipment (ATE) industry doing to meet the new challenges presented by chip-scale packages?

For the most part, a number of individual companies are presenting point solutions to some key customer problems. A few are starting to put together working partnerships to take advantage of some of the new opportunities available in ways that would not have been as likely three to five years ago.

Chip-scale package processes tend to lend themselves to an integrated process line approach. This flow needs to include test as well as the more classic assembly process steps to be truly efficient.

Integrating a full piece of ATE into a process line can be a pretty large task for any one vendor to take on. For instance, Amkor Technology, Credence and FICO have teamed up to put together a matrix test and handling solution for memory devices that required core engineering modifications to the products and processes that all three provide.

Lead inspection, marking, marking inspection, lead repair and packaging can be linked with the parts handling mechanism, creating a modular, multi-functional workcell unit.

The beauty of using workcells to configure manufacturing flow is their modularity, which allows them to be assembled any time and any place to continually replicate proven manufacturing processes around the world.

What progress is being made in establishing standards for test hardware?

Test hardware standards and progress is practically an oxymoron. The breadth of application of the finished IC devices has seemingly insured that true test hardware standards will not be very meaningful.

In the past, fabs have been equipped on a piecemeal basis by separate groups evaluating individual tools and usually selecting a machine for its particular benefits, without completely considering its relation to other tools. Future fabs will minimize these disparate decision makers and formulate a clear strategy that encompasses all aspects of manufacturing.

On the back-end of semiconductor manufacturing, equipment integration will take the form of test and assembly workcells. Automated workcells combine previously distinct equipment and form synchronized, plug-and-play modules. This holistic approach to manufacturing is expected to yield improvements in throughput and overall cycle time, while optimizing cleanroom floorspace, power and peripherals.

From an ATE perspective, the test floor should achieve the closest practical simulation of how the equipment will be used in its end application. Integrating probers and handlers to interface directly with the tester produces this proximity.

Continuing the integration throughout the back-end process by incorporating adjacent functions, such as lead inspection, marking and mark inspection, defines the workcell.

More progress has been made in some of the language developments, such as STIL (standard tester independent language), but this has not had a large number of field deployments yet.

An additional area of opportunity is the sockets for testing in the package. All of the different sockets for the same package seem to have, in many cases, incompatible pad layouts.

What are the future hardware trends in final (parametric and functional) test that will affect IC producers and assemblers?

In general, test will become more distributed from the silicon design stage to the final assembly line. Two examples are built-in self-test (BIST) features for some of the high-performance memories, such as Rambus, and in-line test strategies such as matrix.

The equation denoting where certain aspects of test should be performed will be constantly evaluated and altered from here on out. This will help keep the cost of ATE from skyrocketing. IC producers and the test and finish industry, do not wish to pay millions of dollars per tester, so compromises will be made to keep the acquisition cost of ATE at a moderate level.

What ATE software trends are likely to impact IC makers and assemblers?

It will take a while to accomplish this, but pressure from the subcontract manufacturing sector (SMS) will likely force tester companies to offer tester-independent software in a commercially viable form. These subcontractors are growing quickly, giving them a much bigger voice in the marketplace for ATE.

One of the keys to their success is their ability to completely utilize any test capital that they own. This absorption is greatly enhanced if they are able to transport a test program easily from one test platform to another.

This idea, however, has met with a fair amount of resistance because of the possible negative impact it has on a particular vendor's market share. However, as the SMS companies get stronger, their view is likely to prevail.

The trend of system-on-a-chip will also have a major impact on the software that ATE suppliers will need to provide. As the industry pushes to greater and greater design reuse, test reuse will also become a major issue.

What should assembly and packaging engineers know about testing CSPs?

Because of the time it may take to retool a facility to test CSP-encapsulated devices, packaging engineers need to work on the test handling and fixturing very early in the process design. Spending more time with the test engineers at the beginning of the project—where process flow as well as test flow can be affected—greatly reduces the chance of a catastrophic delay in implementation later.

For example, assembly and packaging engineers may have the most complete knowledge of material handling, and therefore, believe that the test handling issue is a subset of that.

This view, however, will exclude the test engineers' outlook on the electrical performance of the test interface, the acceptable distance from test head to contactor, the software communications issues of material handlers versus test handlers and many other issues that can drag a project out for months if not addressed with the design of the assembly process.

There are also opportunities that can be derived from proper placement of device marking and test within the flow that are different from the era of testing larger, singulated packages in a non-integrated flow.