March - April 1999
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Is Your Chip-Scale Package Really "Testable"?
Before you answer what may appear to be an obvious question, you'd better read this!
By Jack Kessler, Guest Editor
Test is the last thing you want to be concerned with, whether you're producing CSPs or simple SO packages. In fact, test is the last thought on anyone's mind when it comes to designing and manufacturing a semiconductor package.
In fact, it's this last minute and seemingly complete lack of interest in the test cycle that conprises one of the main reasons for the costs, delays and myriad problems normally associated with IC testing.
Worse, as package sizes and pitches decrease, test promises to become even more of an issue. Any of us who are attempting to use and test CSPs are very much aware that test severely impacts the cost and volume of CSP and near-CSP packages.
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| Figure 1. Packages shown, clockwise from top, are Amkor's caBGA®, Amkor's fleXBGA®, SON 8-lead caBGA®, SON 32-lead caBGA®, and flip-chip BGA. A TSSOP 8-lead is at center left, while a SON 8-lead (SON=SOIC no lead) is at center right. |
The key, however, is to address the issue with the first click of the mouse in your CAD program. Many of the pitfalls in testing standard leadframe packages are either not an issue or can be readily overcome through package design.
The need to be proactive and address test requirements during new package design is becoming rapidly apparent and will become even more significant as grid array packages, especially CSPs, replace conventional leadframe formats.
To identify the solutions, we first need to understand the problems. Let's look at a few of the problems that are specific to testing and test handling.
Everything listed in Table 1 translate into two critical words, cost and delay.
The cost involved is for testing, inspecting, handling and shipping new packages with last minute notices and "work-around" solutions. It also includes lost business due to missed deadlines.
The delay occurs in bringing new packages to market while new trays, sockets, handler kits or new handlers are being designed and tooled. Further delays are likely to occur from the last-minute rush involved in redoing tooling or installing short-term fixes that end up as final solutions.
As the demand for smaller, faster, cheaper packages increases, so too will test problems and delays which will logarithmically increase if not addressed in the early package design stages. Test will continue to be the major deterrent in reducing overall semiconductor costs and cycle times.
Table 1. Testing and Test-Handling Problems
- Test handling is dependent upon package dimensions and design. This includes the width, length and thickness, as well as any variations of package outline and edges.
- Mold parting lines, flash, debris from the singulation process and variations due to singulation tool wear can reduce handling accuracy and contactor life.
- The smaller the package and finer the lead/ball pitch, the more difficult it is to move, locate and contact the package at test.
- Assembly tooling tolerances are not in direct proportion to package size. Thus a 0.001 inch variation on an 18-lead SOIC is totally unacceptable on an 8-lead TSSOP.
- CSP's, as a rule, are tested, inspected and shipped using trays as the carrier medium.
- Tray handlers (pick and place), used for most area array packages, are up to five times slower than a tube (gravity-fed) handler. Each package design and vendor requires custom tooling for handlers, trays and sockets.
- Delivery times for tooling of trays, handlers and sockets can exceed the life of the package„or at least the device or product packaged within.
- Test tooling has traditionally been designed after the customer has accepted and been shipped qualification samples of the package.
- Each and every die type requires a custom test program.
- Each semiconductor type, i.e., memory, digital or linear requires a specific test system and hardware to connect to the parts handler.
- The incoming inspection of the PC board or substrate used to manufacture the new CSP and BGA packages is limited to mechanical inspection only.
- You pay for all electrically defective sites on substrate.
- Your customer pays for good die bonded onto defective sites.
- Many grid array packages are untestable by major vendors of final board-level testing due to substrate design and layout.
OK you ask, where is this leading? What's the big secret? Why doesn't the test industry just get its act together? (Which, by the way, is a very good question, and one which I have asked repeatedly, but not always to my benefit.)
What's wrong with my package and board designs as they are? Why is it critical that I know when my factory or vendor converts to strip test in the future?
Now that we have identified the key problems, let's see what package design and assembly can do to help resolve some—if not all—of the test issues related to the packaging, strip design and assembly processes (Table 2).
Design and Process Considerations
As you can see, there are more than a few design and process considerations that can and do have an impact on testing.
These include test and inspection of the incoming PC board all the way to testing and inspection of the final molded product, whether in singulated or strip form or mounted on the final PC board. What you must keep in mind is that the assembly and package groups are not isolated operations. The decisions made in assembly can have very costly impact on the processes that follow.
Table 2. Cost and Cycle-Time Impact in CSP Assembly and Test
Below are most of the items that can have severe cost and cycle time impacts for both manufacturer and user in the assembly and test of any CSP:
- The design of plating tie bars can ease electrical singulation. Ideally, the substrate vendor will etch the plating bars off as in a standard PC board process.
- Specify that incoming PC boards for CSP manufacture be electrically tested for shorts and opens as well as visual defects.
- Reduce overall PC board cost and yield loss by identifying good sites before starting assembly processes.
- Be aware that ground planes and power buses can interfere with popular testing methods (such as HP's TestJet) for completed PC boards.
- Placing ball pads far enough away from edge of the package enables lower cost tooling for sockets, trays, tubes and decreases handling and shipping costs.
- Controlling dimensions from edge of package to the first row of balls can improve yield due to socket placement accuracy. (See Figure 2)
- Enlist test staff inputs on designs for high frequency or noise sensitive device packages.
- Keep coplanarity to an absolute minimum. Less variation results in higher test yields, less damage to the balls and contactors.
- The lowest cost assembly process may actually end up costing more. Low cost usually means loosest tolerances, which translates into higher test costs due to reduced yields and increased tooling complexities.
- Work to tighten JEDEC specs on packages to reduce handler and carrier tooling variations. Even though tradition states that each vendor needs to do it "their way," and processes are based on this, it's cheaper in the total picture to reduce the differences from vendor to vendor.
A bright note: Some of the critical items noted in singulated testing are no longer a problem in strip testing, such as mold flash on leads, lead form variations, package edge to ball centerline, as well as package sizes and variations from vendor to vendor.
Strip-Based Handlers Can Save Money
The strip format used in the manufacture of CSP's, whether rigid or flexible PC board-based, readily lend themselves to being tested in the substrate or strip format prior to singulation.
This can result in test savings up to 60% over conventional singulated testing. Flexible laminates are especially suited to this concept as they are relatively simple to singulate. The molded array CSPs, whether Motorola's MAP BGA or Amkor's caBGA, are more difficult to singulate.
The "chip and molded array" package designs require sawing or water jet cutting to singulate. This may change with future designs and processes, but is presently a draw back to doing strip testing in the United States unless a wafer saw is readily available. Table 4 offers a list to put on your office wall where you will see it every day.
Table 3. Reducing Assembly and Test Costs
- Edge of package to outer row of balls is not an issue, since sockets are not used.
- Placing pads right up to edge of substrate is also a non-issue, since trays and tubes are no longer needed for testing.
Package size and vendor variations are of little impact: test handling is strip based and no longer package dependent, greatly simplifying handler design.
- Parts must be electrically, but not mechanically, singulated prior to testing, requiring removal of plating buses prior to test.
- Ideal substrate design would have packages placed on the same pitch as ball to reduce contactor design. For example, a fully populated single pitch contactor would work for any number of packages and balls, since pitch across the substrate remains constant.
- Coplanarity over a 2 inch x 2 inch area can become an issue if in excess of 4 mils (0.004"), for some contactor designs.
Developing multi-site testing strategies with test staff, customers and vendors is critical.
- Matching test UPH, from a single handler with your fastest assembly process is no longer an issue for most device types. Other low pincount (<68 leads), low cost, high volume device types will follow.
- Review possibilities of testing prior to ball attach. This can reduce burn in times as well as extend contactor life by as much as 25%. Ball attach after test is being done today on large pincount BGA packages.
- Look at inserting test, such as open/short testing in your assembly site. This can provide you with instant feedback on all of your assembly processes.
- Reductions of up to 60% of test costs and cycle times are readily attainable by testing prior to singulation at the assembly site.
- Lead times and costs for tooling for handler kits, trays and sockets are no longer an issue, since they are not needed for strip testing.
- Strip test almost demands high volume, low pin count (<64 leads) and low cost (low ASP) device types but will find other uses.
- To ensure the success of a package design in spite of low cost per pin, size and performance, everyone involved in design, assembly, test and inspection should keep the following in mind:
- The more difficult a package is to test, the less likely its success in the market.
- Test is, and has been, the gating item in total volume of any package, not fab or assembly concerns.
Waiting until the customer is ready to qualify a package is 3-6 months too late to begin considering test methods and equipment.
- Package design and assembly processes must address the need to test on all new and existing products.
- Test costs can be greatly reduced with proper attention to a few key items in package design and process flows.
- "Testability" is the responsibility of everyone, from device designer to package designer to assembly engineer to test engineer and all the jobs in-between. Commitment to take responsibility can better ensure the acceptance and success of new packages.
- Involve test, whether internal staff, handler vendors or a qualified consultant in all new package designs. Their input may save you a lot of embarrassment when your customer cannot test or qualify your new package. Not to mention the millions of dollars and months of man hours spent in development and tooling.
Jack Kessler is owner of Concepts Unlimited, a consulting company specializing in test, assembly and tape-and-reel equipment design and processes.
With his 25 plus years in test and assembly, he brings a unique insight and understanding of the impact they have on each other.
Prior to Concepts Unlimited, he was director of advanced test technology at Amkor Technology, where he was responsible for developing new strategies to reduce test costs and to integrate test in assembly processes.
During the last three years, he has been one of the most vocal proponents of converting from singulated to strip testing, and is credited with making the industry aware of the concept, equipment and equipment design and the payback and need for strip testing. Readers can contact him at jkess@email.msn.com or by phone at 408.725.8698.