A Visible Way to Use Chip-Scale for Discrete Devices

By David Francis and Linda JardineInternational Interconnection Intelligence, Montara, Calif.

Patent Number: 5,753,537

Assignee: U.S. Philips Corp.

Inventors: R. Dekker, H. Maas and P. Versleijen

Title: Method of Manufacturing a Semiconductor Device for Surface Mounting.

SPs are the next step in the packaging evolution, and various designs have been applied to memory ICs and similar devices. Most of these devices are physically large compared to the much smaller dis-crete devices and simpler linear and digital ICs. Applying current CSP technology to these smaller and lower cost devices has not been particularly successful. However, the concepts described in this patent appear to offer a viable solution for housing low cost diodes, transistors, FETs and smaller ICs in low cost CSPs.

One reason this approach results in an inexpensive method is that all processing is done at the wafer level, which eliminates the need to handle any bare die until it has already been packaged.

Frontside Processing

The process begins with a wafer of n+ silicon material, which is processed in a normal manner to form diodes, transistors, FETs or ICs. An epi-layer with an n- doping is formed on the top surface of the silicon wafer. The various regions that become diodes, transistors and other semiconductor elements are formed within this epitaxial layer.

In the diode example, shown in Figure 1, a p+ region is injected to form the PN junction of the diode. The areas between the active regions and the leads are covered with a silicon oxide or nitride thatlater acts as a stop when the wafer is etched from the back side.

An external contact is formed by depositing an n- doped area in the epi-layer to form a contact to the back silicon material. A conductive trace of Ti/Pt/Au is formed between the diode and the external silicon lead.

To protect the front surface of the device from scratches or other environmental damage, a layer of silicon nitride is applied to the entire surface of the wafer.

The front side packaging consists of bonding a suitable stiffener to the wafer's front surface. Since the bulk of the silicon material is subsequently removed, the frontside stiffener must provide the necessary support and other properties required of the final device.

Although a ceramic plate can be used, glass is the preferred material. TCE is not a problem because the stiffener plate is bonded to the wafer using a UV thermoset which is cured through the glass. The UV adhesive has no solvents and therefore outgassing and void entrapment is not a problem.

Since glass has a smooth surface, it provides adequate support to the wafer during the backside removal operation. Since the UV adhesive is also transparent, it is easy to align the wafer for sawing and other processing steps.

Silicon Removal

The wafer is inverted to remove most of the n+ bulk silicon layer. The most suitable process is to use a combination of grinding and atmospheric downstream plasma etching. This step results in a major enhancement in device performance, particularly at high frequencies, since the capacitance to the substrate is greatly reduced.

Once the bulk of the n+ silicon has been removed, backside contacts of Ti/Pt/Au are deposited and patterned. This metallization layer forms the mask used to etch the remaining silicon between semiconductor elements and contacts.

Isolation

With Au as the top metal layer, the remaining silicon between islands is removed. Atmospheric Downstream Plasma (ADP*) or wet etching can also be used. The angle of the silicon formed by the various etching processes is approximately 54 degrees. The silicon oxide layer on the top surface of the wafer acts to stop the etching process.

The result is that each semiconductor device is isolated and connected to an output lead via a conductor and a doped, vertical silicon contact.

The final packaging step involves sawing the wafer into individual units.

No lead frame, bonding wire or other package components are used. The package leads are directly formed on the backside of the semiconductor device. Due to the thinness of the n+ doped silicon layer, the ohmic resistance of the leads is very low.

Figure 1. Front Side Semiconductor Steps. For simplicity, only a single diode semiconductor element is shown.

Figure 2. Front Side Packaging Steps.

Figure 3. Back Side Silicon Removal and Metallization.

Figure 4. Isolated Silicon Islands and Separating Devices. Summary

Since standard IC technology is used for all critical steps in this process, the surface mount devices made using this technology can be produced at very small dimensions. The devices can be placed on solder paste or soldered areas and connected by reflowing.

By employing the proper design, the devices can be made equivalent to other surface mount devices such as a 0402 SMD (0.040" x 0.020" x 0.020").

*ADP (Atmospheric Downstream Plasma) etching is a proprietary process of Tru-Si Technology Inc.

International Interconnection Intelligence is a market and technology research company specializing in the semiconductor packaging and interconnection areas. Contact David Francis or Linda Jardine by e-mail at iii1@ix.netcom.com or by phone at 650.728.5270.