March - April 1999 - ChipScale Review

March - April 1999


eMail the Editor

A Look at Major European Chip-Scale Package Suppliers

Siemens AG, as a major semiconductor supplier, takes an active part in the CSP arena, and has developed a fine pitch BGA for logic devices.

This package is a rigid carrier CSP using wire bonding and overmolding. It is 1.5 mm thick and will be available for pincounts between 48 and 200 with a pitch of 0.8 mm. The processes have been qualified and mass production is scheduled for the 2nd quarter; daisy-chained parts are already available. For higher pincounts, the roadmap forecasts a thickness of 1.2 mm and a pitch of 0.5 mm.

Microelectronic Packaging Dresden GmbH (MPD), is offering contract chip-scale package assembly for small and medium quantities with a rigid carrier CSP using wire bonding technology.


Figure 1. Schematic of CSP from MPD showing stacked chips

Since the carrier is attached on top of the die, no throughholes are required in the carrier. The technology was developed within a German CSP project and is the base for the stacked multi-chip CSP of MPD. The 3D MC-CSP combines flip-chip technology with wire bonding (Figure 1). With this approach, the required board area can be smaller than the total area of the dice and the packaging cost can be reduced with respect to two individual packages. BuS Elektronik is a member of the national German CSP project called "Chip-Size Packaging in Microsystems Technologies."

The project began in 1997 with the goal of establishing CSP know how in Germany. An "electronic gramophone" was developed during the project (Figure 2). The electronic gramophone employs commercial flash memories in a CSP.

Utilizing CSPs instead of TSOPs, the board size can be reduced by a factor of 0.54. The modules are assembled on a conventional SMD assembly line. The cost of the module is comparable to conventional technology. This sample shows that it is possible to implement CSP on-board assembly without major difficulties.


Figure 2. "Electronic gramophone" utilizing Flash CSPs

EM Microelectronic-Marin, a Swiss company (part of The Swatch Group Inc.), located in Marin near NeuchÅtel, is well-known for its gold bumping services, because wafer bumping was initially developed to satisfy the form factor needs of the watch-making industry. Gold bumping is now also widely accepted as the ideal process for chip-on-glass interconnections (e.g. cell phones) or for RF-identification devices, serving, for example, the automotive industry with devices to stop and halt stolen cars.

EM is adding a new wafer-level process to expand interconnection capabilities. This ongoing innovation is driven by the demand within The Swatch Group for products like advanced watches, pagers and micro-controllers. The growing complexity and performance of portable equipment, with the need to keep system cost down, is a driver for solder bumping, a process which has been placed in production at EM. -J. Simon, A. Schubert and H. Reichl



Chip Scale Review o 7291 Coronado Drive, Suite 8 o San Jose, CA 95129 o Email: editor@chipscalereview.com



Sidebar, 6/3/99, 99/06/04, ID=9903/simon2
Keywords=ds00 bb00

© 1998 ChipScale REVIEW