Current Issue An Independent Journal Dedicated to the Advancement of Chip - Scale Electronics April 2001 Email the editor

By W.D. Jordan, Plastronics Socket Co., Irving, Texas

As operating wattages have increased for ICs requiring burn-in, the industry has been forced to enhance heat transfer from the basic IC/package to the burn-in environment. Indeed, in some applications involving very-high-speed microprocessors, waste heat may well exceed 20 watts. At this level, liquid or another method of cooling, is required during dynamic burn-in.

For lower wattage ICs (1-20 watt range), burn-in can be achieved using passive heat sinks and non-refrigerated air. Heat sink size, ambient temperature and velocities can be determined for a given IC burn-in temperature and power level using the general energy and heat transfer relationship common to thermal analysis.

The author searched the literature for a comprehensive discussion of the heat sink size, air temperature and velocity required for chip burn-in at power levels in the 1-20 watt range, but did not find the subject addressed.

Indeed, there was no literature that covered chip-cooling enhancement during burn-in to any great extent. This paper attempts to cast the problem in the overall burn-in framework and allows trade-offs involving IC/package power, approximate heat sink size, ambient temperature and air velocities. IC/package size considerations are also discussed, since they are related to the thermal interface between the IC/package and the heat sink.

Analysis

When we consider the dynamic burn-in process, the customer requirement is a specified chip temperature and burn-in period. Generally, the higher the specified chip temperature, the shorter the burn-in period, since failure rate or meantime before failure is directly impacted by these two criteria.

As a general rule, allowable burn-in conditions are much more severe than end-use applications. The problem of cooling chips during burn-in, however, is not as severe as cooling for end-use applications. For example, in a typical application, the maximum chip temperature may be 125°C for a power device or 95-100°C for a microprocessor.

During burn-in, however, the specified chip temperature may be as high as 160°C. Additionally, the air velocity in most end-use applications is generally in the 200-400 linear feet per minute (LFM) range; during burn-in, it may be 500-1000 LFM.

The ambient temperature in most end-use applications is in the 40°C range. During burn-in, this level or somewhat lower temperatures can also be easily achieved by using non-refrigerated ambient air. Hence, the temperature potential, (chip-to-air) during burn-in will generally be higher than end-use applications, which result in a smaller heat sink for burn-in cooling than required for end-use applications.

Figure 1 represents a typical burn-in oven widely used today. The First Law energy balance at the system boundary under steady-state conditions (Mi=Mo) includes the chip dynamic wattage, any supplemental heat added, box leakage, and the energy (enthalpy) in and out due to mass flow crossing the boundary.

Generally, in higher power applications, the significant terms in the energy balance will be the air enthalpy in and out plus the dynamic chip wattage. The fan energy, leaked energy and supplemental heat are negligible. Therefore, the equation that embodies the major elements for the system energy balance is:

(1)

Figure 2 shows a chip internal to the system and the associated energy balance on the chip itself if the chip has a heat sink attached. The heat transfer between an individual chip and ambient air is:

(2)

Where Ta is the average air temperature flowing over the chip/package heat sink, the energy balance of the air is:

(3)

Equating (2) and (3) and writing the thermal conductance, Uc-a, in the typical electrical analogy gives:

(4)

Where Mc is the mass flow rate over a single chip and the thermal resistance Rc-s is the sum of both the package internal thermal resistance (if the chip is packaged), plus the thermal interface resistance between package and heat sink structure.

For packaged ICs, the manufacturer should specify the chip-to-package internal resistance (often referred to as the θj-c ) for the device. If the chip is bare, then Rc-s is only the thermal interface resistance between chip and heat sink.

Interface Resistance

This interface resistance (IR) is the most difficult to quantify in determining the entire cooling analysis, because it is a function of many variables including the area in contact, joint pressure, joint materials, etc., and has never yielded to extensive analytical analysis with any degree of accuracy.

The IR is a laboratory-measured quantity, and, as a rule, is only repeatable within about ±20% from test to test. The literature on interface resistance, both measurements and analytical treatments, is extensive. The best method of obtaining the IR is a carefully conducted laboratory experiment for the specific application. Even then, the number may vary about ±20% in repeat applications.

Figure 3a shows measured IR for a unit area (1 in 2) of contact verses the joint pressure in lbs/in2. Note that one curve is for silicone grease in the joint, while the other is for a bare joint. The author, who participated in the tests producing these curves, feels that they are reasonably accurate for analysis purposes. The test samples had contact areas of about 0.5 in.(2), which is typical of devices and packages.

Figure 3b is based upon the data of Figure 3a, but shows the thermal IR °C/W as a function of contact area in the 15-20 PSI joint pressure range, typical of joint pressures in applying heat sinks to bare chips or packages using spring clips or similar simple mechanical means of attachments.

In examining Figure 3b, note the various square chip dimensions designated along the ordinates corresponding to the chip or package area. Clearly, for chip or package sizes below about 13 mm square, joint resistance increases dramatically with reduced contact area.

One might choose to overcome this problem by using a heat spreader. Remember, however, that this approach will introduce another interface. Hence, it is probably more advantageous to use the spreading capability of a thicker-based heat sink.

Figure 4 illustrates a wide spectrum of typical aluminum heat sink volumes versus heat sink thermal resistance, Rs-a; the curve parameter is air velocity. This illustration is a reasonable estimate of the heat sink performance (°C/W) for a given heat sink size (volume).

The figure was produced by surveying a wide spectrum of available heat sinks from leading suppliers and plotting performance versus volume. In effect, Figure 4 includes test points gathered from a wide variety of heat sink designs. While the majority are extruded aluminum, some are stampings and pin structures. This figure is representative of what one can expect from well-designed heat sinks for cooling semiconductor packages.

Clearly, the curves shown by Figure 4 did not pass through all points. However, individual deviations from the curves were typically in the ±10%. The above discussion covers Rc-s and Rs-a introduced in equation (4) sufficiently to proceed with a further examination of equation (4).

Equation (4) includes the term Ta that arises from the heat transfer relationship between the air and heat sink. The air approaches the heat sink at Ti and as the heat is removed from the structure, the air is heated and leaves the structure at To.

Temperature Calculation

This average temperature could be calculated by several means, some more analytically rigorous than others. For example, the log mean temperature or the arithmetic mean (To+Ti)/2 could be used for Ta. However, the air temperature rise over the heat sink will generally be relatively small and the outlet temperature, To, can be used for Ta without great error.

Indeed, substituting To for Ta is conservative, because it results in a lower thermal potential for the heat transfer relationship, and it allows great simplification of the mathematical model. Using the arithmetic mean, i.e., (To+Ti)/2 and defining ( Δ=(To-Ti) ) reduces equation (4) to:

(5)

If the outlet temperature, To, is substituted for Ta, equation (4) becomes:

(6)

Both of these equations are very interesting in that if the chip burn-in temperature, Tc, the air inlet temperature, Ti and the temperature rise, Δ, in cooling the chip/ package is specified, then the right hand side of both equations is constant. This indicates that once Tc, Ti and Δ are selected, the product of the air mass flow rate and total thermal resistance chip-to-air is a constant, that is:

(7)

At first glance, equation (7) appears somewhat misleading. It says that if the mass flow rate increases due to air velocity, then the total thermal resistance, Rc-a, is reduced, requiring a larger heat sink.

This is somewhat contrary to one's intuitive thoughts. However, it occurs because once the air temperature rise, Δ, is fixed one has fixed the dynamic heat load for a given mass flow rate, or vice versa. Therefore, the product, Mc Σ Rc-a, becomes a constant.

Figure 5 shows a plot of equation (5) and (6), where the product Mc Σ Rc-a is plotted versus the air temperature rise, Δ. The chip temperature is 160°C and two air inlet temperatures are parameters. The figure also illustrates curves using To for Ta as well as the arithmetic average, and, as noted, there are no significant differences in the Mc Σ Rc-a product when the temperature rise, Δ, is in the lower ranges.

Therefore, for further discussion, and because using To for Ta yields a conservative calculation, equation (6) will be used in further calculations.

Discussion

During burn-in, the objective is to hold the chip temperature at a specified and constant value. This goal can obviously be more easily accomplished if the air temperature is constant; however, this is not possible, since the air will be heated by removing the dynamic thermal energy.

To avoid a wide disparity in air temperature, the cooling air temperature rise, Δ, should be rather small, probably no more than 10°C or less. It is also intuitively obvious, as demonstrated by Figure 5, that the lower the air inlet temperature, Ti, the larger the product of mass flow rate and overall thermal resistance-which implies a smaller heat sink.

Consequently, for burn-in applications which require air-cooled heat sinks, one should use an inlet air temperature, Ti, as low as reasonably practical. Outside air (in the 30-40°C range) is inexpensive and readily available worldwide, so one would probably use it rather than providing refrigerated air.

Example

Here is an example using the information discussed. Suppose the following conditions are given:

Using equation (6) or Figure 5, we can determine that the required Mc Σ Rc-a product must be

Since we know that the chip dynamic heat load is 5 watts, we can now use equation (3) or Figure 6 to determine the mass flow rate required in order to remove this 5 watt load with the 10°C rise in air temperature.

Figure 6 or equation (3) indicates that 4 #/hour is needed. Since the Mc Σ Rc-a product is 90.78, Σ Rc-a must be 22.7°C/W. This says that the sum of the package internal, joint interface and heat sink thermal resistances must be 22.7°C/W to maintain the chip at 160°C with inlet air of 40°C and a 10°C air temperature rise.

Taking this example further, suppose this is a bare chip application (no internal package resistance) and the chip size is 10-13 mm2. Using Figure 3b, we can estimate the joint interface resistance (no grease) to be about 3°C/W.

Therefore, the heat sink required should have a thermal resistance of 19.7°C/W. Furthermore, using Figure 4, we can determine that the approximate heat sink volume would be about 0.13 cubic inch or about 1/2 * H ∞ Ι Φ the air velocity was 250 LFM. If the air velocity was increased, the heat sink volume could be decreased.

In the example above, if a higher-performing heat sink or a higher mass flow rate than that determined by equation (3) and (6) is used, the air temperature rise, Δ, would be lower than the 10°C that was constrained in the example.

Suppose the burn-in customer for the above example indicated that he did not want to burn-in the chip at 160°C but wanted 100°C, and all other conditions remained the same. Using equation (6), we calculate that the Mc Σ Rc-a product is 39.46°C #/w-hr. Since the mass flow rate is 4 #/hour for 5 watts (prior example), the required total thermal resistance is:

In the example Rc-s uses 3°C/W, hence, the maximum heat sink resistance would be 6.86°C/W, which, using Figure 4, requires heat sinks of about 0.7 cubic inch at 250 LFM or 0.32 cubic inch at 500 LFM. If 250 LFM were the air velocity, the 0.7 cubic inch heat sink would be about .9 * .9 ∞ .9.

However, at 500 LFM, the volume would be about .7 *.7 *.7. The above comparison illustrates, however, that lowering the chip burn-in temperature from 160°C to 100°C increased the heat sink volume by a factor of about 5.

Reasonable Limits

In an effort to determine a reasonable but practical limit for air-cooled burn-in using room air and passive heat sinks, we would need to examine the total thermal resistance as a function of a chip dynamic load. Figure 7 illustrates this for Δp = 10°C and Ti = 40°C.

The curve parameter is chip burn-in temperature. Since the example discussed (bare 13 ∞ 13 mm chip) had an IR of 3°C/W, one would think that, generally, the total thermal resistance Σ Rc-a should be at least in the 6-10°C/W range to avoid an excessively large heat sink.

Figure 7 suggests that for a 160°C burn-in temperature, perhaps 18-20 watts would be the highest reasonable power level; at a burn-in temperature of 100°C, the highest power level would be in the 7-8 watt range. The corresponding heat sink volume associated with these numbers would be about 1.1 cubic inches at 500 LFM. Heat sinks larger than about one cubic inch would be unacceptable for board spacing, and further increases in heat sink size lead to longer thermal conduction paths internal to the structure, with smaller gains in overall performance.

Multiple ICs

The discussions and examples have generally dealt with a single chip and heat sink. In the real world, the vendor burns in multiple chips simultaneously. However, whether burning in one or many, the air temperature rise in collecting the dynamic heat load must be rather small, for example 10°C, otherwise there will be a great disparity in the chip temperature, which is unacceptable. Therefore, the above analysis is applicable to multichip burn-in. Clearly, the total mass flow rate should be that determined by the system energy balance equation (1).

System design and chip motherboard layout should avoid passing the same air over multiple heat sinks. Conventional ovens employed today for applications in which the chips have near zero dynamic heat loads offer no obvious advantage for burning-in higher-power chips, and are probably a hindrance.

The ideal situation is a non-oven environment, which would include a large duct discharging a near uniform air stream, and racks containing burn-in boards positioned in front of the air discharge duct. The burn-in board racks would not contain any boards in series; hence, the air will impact every board simultaneously.

This proposal is probably contrary to past practices in the industry, but the author has calculated that a duct exit about 5 °infin; 6 feet could readily accommodate 60-70 typical burn-in boards with 5000-6000 chips. The air mover at 20 watts per chip needs to deliver about 15,000 cubic feet per minute (CFM) air movement at discharge. This movement could be accomplished by an off-the-shelf 10 HP blower at a cost of about $2000.

Filtered Air

With this arrangement, filtered air should be used. If outside air is pulled in to feed the blower, some means should be provided for discharging it outside to avoid overheating the room while maintaining an acceptable back pressure on the system.

Conclusion

My analysis indicates that as dynamic power levels for chips increase during burn-in, the process will require passive heat sinks and reduced ambient temperature. Furthermore, to assure a consistent stable chip temperature, the air temperature rise, in removing the heat load, should be rather small, probably 10°C or less.

Using one cubic inch as the maximum limit, the discussion indicates that the dynamic heat level is probably limited to 18-20 watts/chip and 7-8 watts/chip for a maximum chip temperature of 160°C and 100°C respectively. If the heat level is beyond these levels, one will probably resort to liquid cooling or perhaps refrigerated air with the attendant problems associated with them.

Symbols

W.D. Jordan Mr. Jordan, a licensed professional engineer in Texas, is a thermal consultant to Plastronics Socket Co., Inc. He earned an undergraduate degree in engineering from Tennessee Tech, followed by graduate work at the University of Alabama. He also holds an MBA from Pepperdine University. He worked in the aerospace field for several years as a thermal analyst. He held several management posts at Thermalloy, and served as Thermalloy's president for 16 years before retiring. [wdjordan@home.com]