As expected, the shear strain is equal to 0 at the neutral axis (central solder ball), and increases slowly until the second-to-last solder ball (to a value of about -0.025 percent), after which the outermost solder ball has a much higher value of -0.14 percent. The outer solder ball therefore has the highest thermal strain, and this plot shows the importance of the copper stiffener. As is evident in Figure 5, the fringe boundaries are often poorly defined, which makes extraction of accurate displacement data difficult. For this reason, phase-shifting moiré interferometry was employed and a representative pattern is shown in Figure 7. The phase contours shown in this figure, which are separated by a fringe spacing of 208 nm, provide better-defined displacement contours for the package.
The 3-D FEA U and V displacements in the package along several lateral lines parallel to the PWB surface (along the centerline of the die, along the centerline of the stiffener and along the solder copper interfaces) were analyzed and compared with the moiré results. Stress-Strain Data The inclusion of the experimentally determined stress-strain data dramatically improved the agreement of the model with the moiré results (detailed FEA results will be discussed in a separate publication). The 3-D model (using the plastic properties of die-attach and polyimide adhesive), was next chosen to analyze the deformation of the whole package. Results indicate that the solder balls undergo relatively low strain. The highest equivalent Von Mises stress and plastic strain are located in the upper corner of the solder ball under the diagonal corner of the die. The shear stress and strain in the solder balls are mostly due to the local CTE mismatch between the package and the PWB, which again highlights the importance of the copper stiffener. The FEA result is slightly different than that obtained in the moiré analysis, where the outermost solder ball has a slightly higher strain. This discrepancy may be due to the boundary condition used in the FEA model and the difference in properties of materials at the interface from the films measured.
Flip-Chip Assembly Comparison The deformation of a flip-chip mounted on a PWB was studied using the high-resolution moiré interferometry under the same temperature load (102°C-22°C)(10). Figure 8 is a SEM picture of a flip-chip assembly, which shows a cross-sectional area close to the die corner containing solder bumps, circuit board wiring layers and a solder mask layer.
Moiré interference phase maps are shown in Figure 9. The overall deformation of the flip-chip assembly is similar to that of the CUEBGA, which bends downward upon cooling, but the flip-chip package bends much more than the CUEBGA. For the CUEBGA, the overmold also has larger CTE than that of the die, which tends to make the BGA bend upward upon cooling, thereby canceling the downward bend. Displacement and strain were calculated from the phase maps and plotted along three lines shown in Figure 10.
The solder balls in both assemblies undergo relatively the same shear stress illustrated in Figures 6 (b) and 10. These figures show that the solder balls in both packages undergo very low global shear, which proves that both the copper stiffener in the enhanced BGA and the underfill in the flip-chip assembly effectively reduce the shear stress for the solder balls. For the flip-chip assembly, because the solder bumps are directly connected to the surface of the die, the large CTE mismatch of die and solder bumps makes the solder bumps undergo local shear. The high modulus of the die causes this shear stress to be large.
On the CUEBGA, there is an adhesive layer on the top of the solder balls. Although local CTE mismatch between this layer and the solder balls still exists, the solder balls undergo relatively low shear stress due to the low modulus of the adhesive layer. (Also compare the shear strain values in Figures 6 (b) and 10.) FEA was carried out for an ideal flip-chip assembly with similar dimensions as the CUEBGA. The solder balls in both packages have the same dimensions, but underfill was applied between the die and the PWB for the flip-chip assembly. The FEA results for this ideal flip-chip and two CUEBGA assemblies (one used polyimide adhesive and the other used the proprietary adhesive between the flex circuit and the copper stiffener) were compared. Tables 2 and 3 show the maximum stresses and stress-induced strains, respectively, in solder balls under a temperature load of 102 to 22°C. As mentioned, solder balls in the flip-chip package undergo higher shear stress (σ13 or σ23) due to the severe CTE mismatch between the solder balls and the die. Although the maximum shear stress (σ13 or σ23) in the flip-chip package is only 1.5 times of that in the CUEBGA (Table 2), the maximum shear strain (ε13 or ε23) is much higher than that in CUEBGA (Table 3).
Higher Stresses This result is reasonable because the solder balls already undergo plastic deformation. While the underfill effectively reduced the global shear for the solder balls in the flip-chip package, it also introduced much higher normal stresses (σ11 or σ22) to the solder balls in the ball plane due to contraction under cooling. In general, FEA results indicate that the CUEBGA offers lower solder joint strains than the flip-chip assembly with similar dimensions. FEA also predicts that the CUEBGA construction with the lower modulus adhesive(6) should have better reliability performance than the polyimide adhesive.
Summary Moiré interferometry, finite element analysis and mechanical property measurements were employed to determine the magnitude and distribution of solder ball stresses in a cavity-up enhanced ball grid array (CUEBGA) package. This work is considered crucial for relating geometry and material properties to the board-level reliability of the package, and to help guide future development efforts of the package. Moiré results indicate that the solder ball stresses were low and were adequately modeled using three-dimensional FEA. FEA was then used to compare solder ball stresses of the CUEBGA to a similar sized flip-chip assembly with an underfill. The FEA revealed that the CUEBGA package had lower maximum stresses and strains. Additionally, two different lamination adhesives with different properties were modeled, which revealed that the change to the softer material provided even further reduction of solder balls stresses. The low solder joint stress results reported here are consistent with excellent board assembly level reliability performance measured independently for this same 12 mm CUEBGA package by a leading telecommunications equipment manufacturer. Acknowledgements This work was sponsored by a 3M Foundation grant. The authors thank Dr. Mikel Miller for supporting moiré results of the flip-chip assembly. References 1. K. Norris and A. Landzberg, IBM Journal of Research and Development 13, (3) May 1969, pp. 266-271. 2. J. Partridge and T. Hayden, "Process Design and Materials Selection for Flip Chip Assemblies," Proc. of Intl. Electronics Packaging Conference, Atlanta, Georgia, September 1994, pp. 781-793. 3. Y. Tsukada and Y. Mashimoto, Proc. of Surface Mount International, San Jose, August 1992, pp. 294-299. 4. Prismark Partners, "CSPs-the Fog Begins to Clear," March 1999, pp. 2-9. 5. T. Hayden, P. Harvey, et al., "Performance and Reliability for Cavity-Up Enhanced BGAs," High Density Interconnect (4) April 2000, pp. 22-31. 6. T. Hayden, W. Clatanoff, et al., "Assembly and Package Reliability of a New, Flex-Based Fine Pitch BGA," Proc. of Chip Scale and BGA National Symposium, Santa Clara, Calif., May 1999, pp. 177-183. 7. T. Ejim, S. Gahr, et al., "Attachment Reliability of Chip Scale Packages with Various Constructions," Proc. Surface Mount Intl., Chicago, Ill., September 2000, in press. 8. Developed by 3M. 9. D. Post, et al., "High Sensitivity Moiré: Experimental Analysis for Mechanics and Materials," Spring-Verlag (New York, 1994). 10. S. Dai, and P. Ho, "Thermo-Mechanical Deformation of Underfilled Flip-Chip Packaging," IEEE/CPM International Electronics Manufacturing Technology Symposium. 11. M. Miller, et al., "Analysis of Flip-Chip Packages using High Resolution Moiré Interferometry," ECTC, San Diego, Calif., June 1999, pp. 979-986. 12. ABAQUS 5.8, a registered trademark of Hibbitt, Karlsson & Sorensen, Inc., 1080 Main Street, Pawtucket, RI 02860.
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