While Asia long ago put its stamp of ownership on the business of contract IC assembly, a few U.S.-based companies continue to operate domestically. The two largest now, and probably the best-known, are OSE-USA [ose-usa.com], formerly IPAC in San Jose, and Pantronix Corp. of nearby Fremont, Calif. Both however maintain strong ties to Asia. OSE-USA is owned by Taiwan's OSE, a high-volume packager, while Pantronix also operates mega-plants in China and the Philippines.
Silicon Turnkey Solutions [siliconturnkey. com], smaller than either OSE-USA or Pantronix, continues to operate in Manteca, Calif. STS took over the real estate once owned by the legendary Indy Electronics and then Alphatec, several years ago. While almost every major subcontractor has moved or made plans to site in China, there are still a few content to remain and sell to the U.S. market. One which has kept a relatively low profile, until recently, is Union Semiconductor Technology Corp., a privately held firm. USTC, with 61 employees is working in magnetoresistive RAMs and advanced packaging. The company's advanced packaging group was started by Cray Research to make high-performance packages for its super computers. In 1992, the group began doing government-funded packaging R&D. Although its headquarters are in Plymouth, Minn., in April 1999, it acquired the Silicon Graphics' Advanced Packaging Group and its Chippewa Falls, Wisc. campus. USTC's manufacturing location-near the twin cities of Minneapolis-St. Paul-offers significant benefits to weary travelers, who can now avoid customs, reduce travel expense and eliminate those grueling 16-hour trips to Asia. I spoke recently with David Scheid-the man in charge of USTC's marketing. I wondered, as you must, what the percentage is for another IC packaging foundry to enter the market. After all, after two years of recession, almost every sub is only just now beginning to hold its head above water. Scheid, however, says USTC is banking on its expertise in stacked/3D packages produced through its patented Vertical Integrated Package formula. This is a real space saver. He notes that a two-die stack after folding is only 12 mils thick. To learn more about USTC, contact Scheid at dscheid@unionsemiconductor.com. A Keeper for Your Library Peripatetic speaker, author, inventor, restaurateur (ask him for his superb creamed spinach recipe!) Joe Fjelstad is back with a new book. Chip Scale Packaging for Modern Electronics recently debuted from Electro-chemical Publications [electrochempublications.com]. Joe has been joined in his latest effort by the ubiquitous Dr. Reza Ghaffarian and Dr. Young-Gon Kim of Tessera Technologies. Suffice it to say that if you've never read an article by Joe or heard him deliver a paper at a trade conference, you don't read and/or don't attend conferences. I did not promise Joe a good review when I asked for a copy of his latest tome. I did, however, request an endearing inscription in the front of the book, which he was good enough to supply. The 438 pages are divided into three sections. The first looks at the CSP market and applications with chapters by Jan Vardaman of TechSearch International and Vern Solberg, Tessera's packaging guru. The middle section looks at current CSPs and discusses flip-chip technology. The final two chapters examine stacked packaging and wafer-level packaging. Considering the pedigree of the authors and the extensive ground they cover, this book is a welcome and much-needed addition to anyone's basic CSP library.
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