April 2003 The International Reference for Chip-Scale Electronics, Flip-Chip Technology, Optoelectronic Interconnection and Wafer-Level Packaging Email the editor

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By Ron Iscoff, Editor

Figure 1. This exploded view illustrates the parts of a probe for high-frequency applications. This socket, with less than 0.5 nH self-inductance, is capable of use at frequencies of higher than 10 GHz.

Growing semiconductor device sophistication is driving an expanding market for test and burn-in sockets that operate in the high-speed 10 GHz frequency range and above. Typical applications are in datacom, telecom and next-generation CPUs.

In addition to the usual test complexity of lower-frequency sockets, high-frequency units add such issues as compliance, parasitics and crosstalk.

Socket Technology

Other considerations common to the short or coaxial probe technology employed for many high-frequency sockets include impedance, bandwidth, self-inductance, capacitance and insertion loss (see glossary).

Synergetix of Kansas City, Kan., which employs high-performance spring probes developed by its IDI probe division, has reached frequencies well above the 10 GHz range by developing probes with exceptionally short signal path lengths. (Figure 1 shows an exploded view of a probe for high-frequency applications and a high-frequency test socket.)

"While spring probes provide one of the best travel-to-length ratios available, very short probes inevitably produce fairly restricted travel," according to Jamie Andes, Synergetix' semiconductor product manager.

In turn, he adds, careful consideration must be given to the design of the DUT board, handler and change kit. The board must remain coplanar, "requiring mindful attention to external stiffening, and the handler must be capable of hardstopping directly on the socket without damage."

Nick Langston Sr., product manager for Dimensions Consulting Inc., Santa Clara, Calif., observes that fast data rates have become relatively common in larger packages with 1.27mm pitch between contacts. DCI's answer, he says, is the company's new QuickTurn line, "a relatively standard product at modest cost." (Figures 2-4 illustrate high-frequency test sockets.)

At high speeds, the device contacts have to be very short (sub-2mm) with low capacitance. The major challenge, he says, is for the socket to handle the rise times without generating "horrendous crosstalk."

Figure 2. Ironwood's solderless SG-BGA-6080 socket supports very dense 40mm body BGA devices, utilizing a high-performance elastomer contactor. An integral, aluminum-finned heatsink is designed to dissipate 30W with an optional top-down fan that also provides a compressive force.

Langston says DCI has had to reduce crosstalk in chip-scale and fine-pitch packages, which requires very short pins and a reduction in the diameter of the pin barrel to under 0.005 inches.

The key challenge for high-frequency test is compliance with the burn-in or DUT board, according to David Pfaff, president of Plastronics Socket Co., Irving, Texas.

"To ensure a good connection from DUT to the board, a connector typically needs to handle anywhere from 0.010" to 0.025" of coplanarity issues in the package," says Pfaff.

That means for 10 GHz and above, the contact element must follow a very short signal path while also addressing the coplanarity problems, he says.

A Matter of Compliance

Pfaff says compliant silicon rubber membranes with embedded metal contact elements or super-miniature metal contacts can accommodate high frequencies. However, both rubber or metal contact elements can be problematic, depending on the situation.

The compliant membranes require a high psi-force to allow for coplanarity issues and don't work well above 120°C. Super-miniature metal contacts, he adds, are "very expensive" and require machined housings for proper alignment and retention. Additionally, smaller contacts produce higher metal fatigue.

Figure 3. Exatron offers Particle Interconnect test sockets. The sockets employ metallized diamond particles to form a micro "bed-of-nails" contact. The rough surface created by PI allows for zero lead length interconnect of DUT leads and testboard circuits, ideal for RF testing, the company says. The resulting contact offers a resistance of less than 3 milliW.	Figure 4. Emulation Technology's "Silver Wings" solderless BGA socket system operates at up to 9 GHz bandwidth. The system enables the user to test, debug or program any BGA or µBGA package, regardless of lead pitch ball count, grid size or package size combination.

Brandon Bailey, product manager for R-Tec Corp., Meridian, Idaho, emphasizes that interconnect technologies with shorter signal paths and excellent electrical performance "often have a fixed or limited range of compliance and lower tolerance for coplanarity mismatch."

Bailey says a compliant or articulated compression block is often needed to create an orthogonal presentation of the DUT to the interconnect device.

Sufficient and repeatable compression is another design constraint for high-frequency interconnection. "This needed compression can be achieved through the use of a built-in hard stop, which ensures that sufficient force is applied to each DUT without the risk of overcompression or damage to the high-frequency interconnect."

Material selection by socket producers is another important consideration, says Bailey, since material expansion over temperature will affect the quality of the connection and introduce unpredictable (and unacceptable) electrical results in high-frequency test.

Bailey admits that testing at 10 GHz and above presents challenges, but he adds that "companies with a thorough understanding of the interconnect technologies embedded in their sockets can create products that will produce highly repeatable results in multiple environments."

Multi-Chip Packaging Systems Pose New Test Challenges for the Industry

Until wafer-level burn-in becomes a reality, the emerging multi-chip packaging industry needs practical solutions that screen for reliability and performance. By Dr. Tom Di Stefano,Centipede Systems, San Jose CSPs and their wafer-level cousins face increased demands for performance and reliability driven by the boom in multi-chip packaging. Early stacked CSPs were rather simple affairs aimed at cell phones and personal electronics. As multi-chip packaging extends into critical applications, test requirements are becoming more demanding. The known-good die (KGD) problems that plagued MCMs a decade ago have resurfaced with increasingly complex system-in-package configurations. Whether in wafer-level or bare-die form, the chips must be tested for speed and reliability before assembly in the more complex systems. Until wafer level burn-in becomes a reality, the emerging system-in-package industry needs practical solutions that screen for reliability and performance to provide ready-to-mount chips. Screening protocols range from hot-chuck testing to full-scale burn-in. More recently, leading semiconductor manufacturers are exploring more efficient methods including run-in or accelerated test during burn-in. To satisfy reliability requirements cost-effectively, components are being tested under more extreme conditions. One attractive approach is the testing of whole strips or trays of CSP or WLP chips during thermal stress. Two-sided test allows probing of all contact points on a package (Source: Centipede Systems) System-in-Package Applications Reliability and performance at the system level is an additional challenge facing system-in-package applications. Increasingly complex interconnect of various types is being integrated into multi-chip packages introduces new failure mechanisms. Incorporation of a simple circuit board into a multi-chip package ups the ante, as the board must pass the more stringent component level qualification tests. Component testing is beginning to take on several aspects of on-board testing. To meet the demands of system-in-packaging testing, manufacturers are incorporating more sophisticated tests. Two-sided contactor stations allow probing of all contact points on a package. This technique allows detection of defects in stacked and other 3D packages. Centipede Systems' sophisticated electrical tests can find latent defects, such as defective vias or dry solder joints, in the package structure by detecting distortion of signals as they course through the 3D structure. By means of new and innovative test technologies, the industry is finding solutions to the reliability problems inherent in multi-chip systems. Dr. Di Stefano is president of Centipede Systems and a pioneer in chip-scale and wafer-level packaging. [tom@centipedesystems.com ]