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April 2003
The International Reference for Chip-Scale Electronics, Flip-Chip Technology, Optoelectronic Interconnection and Wafer-Level Packaging

Semiconductor Bump Electrodes Offer Stress Dissipating Feature
David Francis and Linda Jardine
Contributing Editors

PATENT NUMBER: 2002/0132461

ASSIGNEE: Casio Computer Co., Ltd.

INVENTOR: Masayasu Kizaki

TITLE: Semiconductor Device Having Bump Electrodes with Stress Dissipating Structure and Method of Manufacturing the Same

There were several reasons for selecting this patent, including the value of the topic to readers. Addition-ally, we wanted to point out to readers that patents that haven't been formally issued after 18 months are published and can be searched just like issued patents.

This patent also illustrates an important point: No matter how good the original idea, it is normally possible to make improvements over time that result in a better product.

When mounting devices such as WLPs or CSPs to laminate substrates, it is necessary to compensate in some way for the TCE mismatch. Typically, the taller the standoff height, the better the device will withstand temperature cycling.

Figure illustrates the original method of stress reduction compared to the improved patent.

Bumps Formed by Plating

In the original process, a copper redistribution layer is deposited on the wafer, as shown in the illustration. Photoresist is applied and patterned so that bumps can be formed by plating. It is desirable to make these bumps as tall as possible, but height is generally limited by the photoresist. A good height is 120µm. An epoxy resin support layer is then applied to the surface of the wafer so that it covers the bumps and is cured.

The wafer and resin surface is then lapped to expose the bumps and to insure a uniform bump height. This typically removes about 30µm of bump height (resulting in a 25 percent loss).

This patent illustrates an important point: No matter how good the original idea, it is normally possible to make improvements over time that result in a better product.

A recess is then formed in the resin by etching the copper columns to remove another 30µm or so of material (another 25 percent loss). A solder ball is then placed in the recess, or solder paste is screen printed and reflowed to form the solder connection.

Due to the processing steps involved, a standoff height of 120µm is reduced to about 60µm as a result of the processing. This significantly increases the strain on the solder joint. Etching further reduces the height and also increases the bump-height variability.

The Invention

The process through resin coating and removal remains the same.

Once the copper bumps are exposed, instead of etching them, a second resin layer is applied by film, screen printing or other method, as shown in the illustration.

This method also allows the hole to be made slightly larger to allow for any variation in position. It also allows the side walls to be formed with a taper to provide better support to the solder ball once it has been reflowed.

Depending on the time between operations, it may be desirable to plate the exposed bumps so that they remain solderable.

International Interconnection Intelligence is a market and technology research company specializing in the semiconductor packaging and interconnection areas. Contact David Francis or Linda Jardine by e-mail at iii1@ix.netcom.com or by phone at 650.726.1380 or 530.274.8536. [iii1.com]

 
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