Singapore—STATS ChipPAC Ltd. announced a new flip chip technology that offers a significant cost savings over standard flip chip packages with price points well below wire bond packages. STATS ChipPAC’s low cost flip chip technology features an innovative routing efficient interconnection structure and a simplified substrate technology design coupled with improvements in assembly technology such as a cost effective mold underfill process.

Although the industry is shifting from wire bonding to flip chip interconnects due to the increase in gold bonding wire costs, STATS ChipPAC has taken an aggressive approach to driving down the cost of flip chip technology. Until now, the high price of substrates and the elaborate and costly underfill step in flip chip technology have been barriers to flip chip adoption in mid- to low-pincount packages of 100 to 700 pins. For IC companies interested in converting their package designs from a wire bond interconnect to flip chip interconnect, the typical industry cost premium has been in the 30% range.

STATS ChipPAC has achieved an unprecedented cost reduction with its low cost flip chip technology, essentially offering semiconductor companies the opportunity to have flip chip technology at price points below wire bond packaging. Rather than focusing on incremental changes in individual materials or processes, the company took a comprehensive approach to reengineering the package structure and key processes to design the cost out of each element of flip chip technology, from substrate design to bump and the assembly process.

“The goal with our low cost flip chip program was to not merely identify ways to reduce the cost of our packages incrementally, but to have a clear breakthrough in fundamentally improving the cost of the flip chip packaging process,” said Dr. Raj Pendse, vice president, technical marketing. “Where a conversion to flip chip technology may have been cost prohibitive in the past, we are able to offer customers an advanced flip chip interconnect solution with a cost effective price point compared to wire bond packaging.”

Since traditional substrate costs average 50% or more of the total package cost, the company designed a new routing efficient interconnection scheme that reduces the substrate layer count and complexity. The 2-layer laminate substrate design has a significantly lower cost than traditional 1-2-1 build-up substrates used for flip chip interconnection. The new substrate achieves equal or higher routing density with the same laminate substrate design rules as wire bond substrates.

The standard underfill process for flip chip interconnect is typically the slowest and single most expensive process step in the flip chip assembly process. In conjunction with the new interconnection and substrate design, they use an efficient mold underfill technology that provides higher process throughput at a lower cost than conventional capillary underfill. In anticipation of the industry’s shift to lead-free bump and halogen-free bill of materials, the low cost flip chip technology has a true lead-free bump composition which has proven to be effective with the mold underfill process.

Dr. Pendse continued, “We qualified the first phase of our low cost flip chip program in 2008 and now are in high volume production with packages such as Fine Pitch Ball Grid Array (FBGA) for mobile applications. As we move into the second phase of our program, through further innovation we are significantly increasing the routing density of our solution without stretching the substrate design rules. As a result, we believe we will be able to offer customers low cost flip technology for more than 75% of real die designs.” [statschippac.com]

Rabat Technopolis Park, Morocco—Nemotek Technologie, a manufacturer of customized wafer-level cameras for portable applications, announced certification of its Class 10 clean room. This state-of-the-art facility is the first in Africa located in the Rabat Technopolis Park, a hub for technology development in Morocco. The facility will serve as the center for the design and manufacture of Wafer-Level Packaging (WLP), wafer-level optics (WLO) and wafer-level cameras (WLC) used in camera phones and other portable devices. With the certification, Nemotek validates its ability to produce world-class silicon wafers in a high-level sterile environment.

Nemotek Technologie’s clean room will reside in a 10,000 m2 facility enabling the company to streamline the manufacturing of wafer-level camera modules and significantly reduce the threat of airborne particles that may cause harm to chips. Particle defects such as dirt or dust on the image sensor surface are the largest factor for yield loss during camera module assembly, with particles on the die serving as a cause for assembly failure. The clean room will streamline the manufacturing process and produce high quality, low defect wafer-level solutions. As customer demand increases, the clean room can be upgraded to a Class 1.

“To become the first wafer fabrication company to maintain a Class 10 clean room facility in Africa is a major accomplishment for us as well as the industry,” said Jacky Perdrigeat, CEO of Nemotek Technologie. “There is a growing demand in the industry for miniaturization without sacrificing quality. We understand this demand from customers to produce quality solutions that are low in defects. With a clean room as part of our manufacturing facility, we are producing materials in a sterile environment and advancing the production of miniature wafers without interference of outside elements.”

Nemotek’s clean room was validated and certified by Luseo, an independent certification company based in France. These certifications are based on the universal standard ISO 14644-1/3/4/5 for clean rooms and associated controlled environments.

Nemotek Technologie manufactures customized wafer-level cameras for portable applications. Established in May 2008, Nemotek is funded by Caisse de Dépôt et de Gestion (CDG). [nemotektechnologies.com]

Bannockburn, IL—The IPC — Association Connecting Electronics Industries, released a new white paper, “An Executive Overview of HDI The Reality of HDI: Fact vs. Myth,” to clarify the facts and misconceptions surrounding high density interconnect (HDI) and dispute the argument that the North American PCB industry cannot produce HDI boards. Developed by the IPC PCB Management Council Steering Committee, the document provides key reasons supporting the manufacture of HDI printed circuit boards (PCBs) and facts regarding the expense of HDI.

The need for HDI is being driven by vital industry demands, including miniaturization, lower costs, and improved reliability. This paper addresses the ways HDI technology adds efficiency and quality in meeting those demands, and presents survey results and analysis of market opportunities as well as information on cost implementation and advantages. The white paper also serves as a starting point for senior level executives in the PCB industry looking to break into the HDI market.

“Manufacturing HDI is critical to remain competitive,” contends Peter Bigelow, president and CEO of IMI, Inc. and chairman of the IPC PCB Management Council Steering Committee. “Research data supports the conclusion that HDI will become pervasive in every application and is already considered to be mainstream technology in many. Yet in 2007, North American production represented only 3.4 percent of the world market in HDI technology. North American PCB manufacturers need to realize that the barriers to HDI can be overcome.”

IPC members can download the white paper for free at www.ipc.org/HDI-Executive-Overview

Durham, NH—Economic research firm e-forecasting.com says the North American Semiconductor Chip Sales leading indicator declined by 0.5 percent to a reading of 164.0, after going down 1.0 percent in February. The index was set to average 100 in 2000. The indicator, comparable to the company’s other global regional semiconductor industry indicators for Japan, Asia Pacific and Europe, is a forward-looking composite index that forecasts six months ahead, on average, business activity in the region for sales for semiconductors.

“The six month growth rate of North America chip sales’ leading indicator continues to stabilize. If this continues in the next few months, hopefully we will see the industry begin to rebound,” noted Maria Simos, CEO.

The six-month growth rate is commonly used in business cycle analysis for both signaling impending turning points in business activity and as a recession monitor. The semiconductor leading indicator’s six month growth rate continued its rapid decline, dropping 17.2 percent in March 2009, after a decline of 18.2 percent the previous month. Consecutive negative values in the six-month growth rate predict an end to an economic expansion and the beginning of an upcoming recession.

Five of the nine components that make up the leading indicator for semiconductor sales in the Americas market improved in March: Productivity Barometer, US Manufacturing; Interest Rate Spread, US Financial Markets; US Housing Market Barometer; Business Activity, US Manufacturers and Long-Term US Consumer Expectations. The four components that had a negative contribution to the leading indicator for semiconductor sales in the Americas market were: Weekly Production Hours, US Semiconductors; Non-US Demand Outlook, 35-Country Leading Index; Change in Profit Margins, US Semiconductors and Ratio of Orders to Inventories, US Electronics. [e-forecasting.com]

El Segundo, CA—Defying a flat year for the global automotive infotainment semiconductor market, leading supplier STMicroelectronics NV managed to achieve double-digit revenue growth in 2008 due in part to the success of its Cartesio product, a combined media processor and GPS baseband chip, according to iSuppli Corp.

The global automotive infotainment semiconductor market in 2008 generated revenue of $3.4 billion, up a scant 0.6 percent from $3.3 billion in 2007. While the average amount of entertainment and informational electronics content in cars continued to increase in 2008, the infotainment industry suffered from a 6.6 percent decline in global car sales for the year. The infotainment semiconductor industry’s flat growth in 2008 contrasts sharply with its 16.8 percent expansion in 2007.

STMicroelectronics massively outperformed the market in 2008, with its revenue rising by 12.6 percent to $439 million, up from $390 million in 2007. The company’s share of global automotive infotainment semiconductor revenue rose to 13 percent, up from 12.6 percent in 2007.
“STMicroelectronics benefited from the strong market acceptance of the Cartesio, with the company notching up several key design wins,” said Richard Robinson, principal analyst, automotive electronics, for iSuppli.

“Due to the Cartesio, STMicroelectronics achieved massive growth in the multimedia/navigation segment of the infotainment chip market, with its revenue in this area revenue rising to $71 million in 2008, up a stunning 1,320 percent from $5 million in 2007.”

Looking at the major segments of the automotive infotainment semiconductor market, STMicroelectronics in 2008 held the leading position in the audio amplifier and digital/satellite radio tuner/decoder segment and was No. 2 in AM/FM tuner/audio processing and GPS navigation receiver areas.

There were no changes in the order of the Top 5 infotainment semiconductor suppliers, with STMicroelectronics, NXP Semiconductor, Panasonic and Renesas maintaining their No. 1 through 5 positions. The combined revenues of the Top 2 suppliers—STMicroelectronics and NXP—accounted for 25 percent of market revenue in 2008, as both companies supply a broad range of automotive-grade silicon to the infotainment market.
Other developments among the Top 5 suppliers in 2008 included:
• No. 2 NXP Semiconductors held on to the second position in overall infotainment semiconductors in 2008 as the dominant supplier of AM/FM tuner and processor chips and the No. 2 maker of audio amplifiers targeted at the automotive space.
• No 4 Renesas increased its infotainment semiconductor revenue by 10 percent in 2008 compared to 2007, maintaining its position as the No. 1 supplier of multimedia/navigation logic with a 20 percent worldwide market share.
•No 9 Freescale Semiconductor was the biggest market mover in 2008 with its revenue up by more than 50 percent from 2007 on the back of design wins with Ford for its Sync system and on the continued growth of the OnStar solution from GM. [st.com] [isuppli.com]

Scottsdale, AZ—17 of the top 20 companies changed positions in 1Q09, with more volatility expected in 2Q09. The global recession and subsequent inventory corrections in the electronic system and semiconductor industries have caused a major shakeup in the 1Q09 top 20 semiconductor company ranking.

As discussed in IC Insights’ May Update to The McClean Report, the volatility in the ranking is forecast to continue in 2Q09. Many top semiconductor suppliers are expected to rebound from a weak 1Q09 to register strong double-digit 2Q09/1Q09 sequential sales growth! Of the top 20 companies in 1Q09, only Intel (#1), Samsung (#2), and Fujitsu (#17) remained in the same positions as they ranked in 2008. Some notable changes to the top 20 ranking are shown below.

Qualcomm, the world’s largest fabless IC supplier, which focuses on leading-edge cellphone devices, moved from being ranked 8th in 2008 to 6th in 1Q09. IC Insights anticipates increasingly positive news for Qualcomm as high-end cellphone (e.g., smartphone) sales pick up speed throughout 2009.

AMD jumped into the top 10 group, moving up three spots from 12th in 2008 to 9th in 1Q09. However, AMD is one of the few top semiconductor companies that has stated it expects 2Q09 sales to be worse than in 1Q09. How long will it stay in the top 10?

MediaTek, a high-flying fabless IC supplier, joined the top 20 ranking by jumping five positions. In fact, MediaTek was the only top 20 semiconductor supplier to register a 1Q09/4Q08 sequential sales increase, a whopping 16% surge. The company attributed part of its success to the “stay-at-home-economy” driving digital TV IC sales as well as continued strength in its core wireless communications business.

TSMC, the largest foundry in the world, dropped six positions in the 1Q09 ranking but managed to stay in the top 10. It is well known that fabless IC suppliers are some of the worst offenders with regard to IC inventory builds and burns. With fabless companies representing the bulk of TSMC’s sales, the company has been caught in a hellacious two-quarter inventory burn period (4Q08 and 1Q09), with 1Q09 sales 57% less than were registered in 3Q08.

However, the anticipated recovery in TSMC’s sales will be one of the most significant rebounds witnessed in the IC industry this year. Using current exchange rates, it is expected that TSMC’s 2Q09 sales will be about $2.2 billion, a sequential increase of 89%! Moreover, IC Insights believes that if this level of sales is achieved next quarter, it would serve to rank TSMC as the third largest semiconductor supplier in the world in 2Q09.

NXP and Nvidia fell out of the top 20 ranking in 1Q09 with NXP falling from being ranked 15th in 2008 to 21st in 1Q09 and Nvidia dropping from 20th to 22nd. [icinsights.com]

Austin, TX—DisplaySearch forecasts the total touch screen module market will grow to $9 billion by 2015, from $3.6 billion in 2008, with a CAGR of 14%.

“Touch screens are becoming widespread due to the ease of use and intuitive interfaces they enable, which can save time and increase productivity. Falling prices have also spurred adoption. Finally, touch screen devices are now perceived as cool and fun,” noted Jennifer Colegrove, PhD, Director of Display Technologies at DisplaySearch. “Touch screen penetration has been rapidly increasing in mobile phones, portable navigation devices, gaming and other applications. Over the next several years, touch screens will undergo strong growth in large-size applications, such as retail, ticketing, point of information and education/training.”

The touch screen industry is extremely diverse, with different companies pursuing several different technologies. There are over a dozen touch screen technologies. Resistive touch screen is the leader in terms of unit shipments and over 60 companies are manufacturing it. However, both surface and projected capacitive technologies have attracted numerous suppliers, and many companies are also pursuing multi-touch capabilities. [displaysearch.com]

San Diego, CA— The 59th Electronic Components and Technology Conference (ECTC) will be held this year from May 26th through 29th in San Diego, California. This international conference is jointly sponsored by the IEEE Components, Packaging and Manufacturing Technology Society (CPMT) and the Electronic Components Association (ECA).

More than 300 high-quality papers will be presented at the conference in 38 oral sessions, two poster sessions and a special student poster session. Authors from companies, research institutes and universities from nearly 20 countries will present at the ECTC. The papers cover a wide spectrum of topics, including electronic components, materials, assembly, packaging, system packaging, optoelectronics, reliability and simulation. The program includes a topic on “Emerging Technologies” to address exciting new developments and applications in printable and organic electronics and biomedical technologies.

New this year is the addition of optoelectronics special sessions on Tuesday that will cover technical presentations on innovations in optoelectronic packaging. In addition to the technical sessions during the day, evening sessions focusing on various special topics will be held on three nights. A panel discussion (Tuesday at 7:30 pm) on “Consumer Electronics in Times of Recession and Recovery” chaired by William Chen will give the audience the opportunity to share views on this specific topic. A plenary session (Wednesday at 7 pm) entitled, “Product Qualification Strategies in the Semiconductor Industry” co-chaired by Jie Xue and Senol Pekin will give an outlook from industry experts on this important topic. Thursday evening is also busy, starting with the Gala Reception at 6:30 pm followed by a CPMT Seminar on “Nanotechnology for Advanced Devices and Packages” chaired by Yoshitaka Fukuoka and Kishio Yokouchi and an Optoelectronics Seminar sponsored by OIDA (Optoelectronics Industry Development Association) on “Green Photonics and Optical Packaging” co-chaired by William Ring and Michael Lebby. Both seminars start at 8 pm.

The Professional Development Courses chaired by Kitty Pearsall will be on Tuesday. World-class experts in their fields offer 16 courses on different topics. The technical program and professional development courses are supplemented by the technical exhibition corner. Leading companies primarily in the electronics components, materials and packaging fields exhibit their latest technologies and products. The exhibitors are hosting a reception on Wednesday at 5:30 pm. [ectc.net]

Edina, MN—The SMTA, in conjunction with Chip Scale Review magazine, confirmed that program planning is on track for the 6th Annual International Wafer-Level Packaging Conference and Tabletop Exhibition (IWLPC) to be held October 27-30, 2009 at the Marriott Santa Clara Hotel in Santa Clara, CA.

This premier industry event explores leading-edge wafer-level, IC and multichip device packaging and substrates/interposers, as well as related test and measurement technologies. There will be special emphasis on the numerous 2D package and 3D stacked chips and package alternatives and TSV vertical interconnect options. The program covers all chip devices and WLP test, assembly and packaging options including HDI interposers and substrates for mixes of ICs, MEMS, RF/wireless, optoelectronic and other wafer-fabricated devices.

The conference expands to three tracks in 2009 with two days of papers covering WLP; 2D/3D stacked packaging; and integrating ICs, MEMS, MOEMS, wireless and photonic devices with novel processes. keynote and plenary speakers will be announced next week. Strong industry support is reflected in the number of participating consortia, R&D institutions and industry groups.

Suggested topics for presentation include wafer level packaging processes; through silicon via (TSV) technologies; 2D and 3D CSP; wafer level CSP (WLCSP); 3D interconnect packaging options; IC packaging substrate and interposers; wafer thinning, bonding and sealing; flexible substrates and embedded passives for ultrathin applications; plating—via fill and redistribution; MEMS/MOEMS WLP Processes; flip chip packages; UMB, RDL and bumping; lead-free technologies and issues; materials advancements; wafer and device cleaning; RF and wireless assembly; solar photovoltaic applications; WLP Markets and Trends WLP metrology and testing; mixed chip assembly issues; CSP WLP designs and processes WL-Enabled Devices; lab-on-chip, MEMS, Bio-MEMS, Bio-Med liquid materials deposition and handling Modeling & Simulation for WLP Multichip packages; and Nanotechnology packaging at wafer level.

Dr. Ken Gilleo of ET-Trends LLC, Warwick, RI (General Chair) and Terry Thompson, editor of Chip Scale Review, San Jose, CA, (Technical Chair) invite abstract submissions for this program. To submit an abstract for this program, a 200-300 word abstracts should be submitted on-line or by email to Melissa Serres Marx at melissa@smta.org on or before June 1, 2009. [smta.org]

Piscataway, NJ—George G. Harman, a researcher at NIST, contributed enormously to wire bonding technology that led to an understanding of the process, and improved its reliability. His work helped transform a labor-intensive, manual procedure into the present automated, reliable process capable of producing hundreds of billions of packaged semiconductor devices/year. The IEEE with the 2009 IEEE Components, Packaging, and Manufacturing Technology Award is honoring Harman. IEEE is the largest technical professional association. The award will be presented on 28 May 2009, at the 59th IEEE Electronic Components and Technology Conference in San Diego, CA.

Wire bonding is a primary method of electrically connecting microchips and other electronics during semiconductor device assembly and packaging, where the wire is connected at both ends using a combination of heat, pressure and ultrasonic energy. The components that make up today’s electronic devices often contain thousands of wire-bonded interconnections to each, carrying the electrical current required to make the devices work. It is estimated that over 90 percent of all semiconductor devices today are interconnected via wire bonding.

Harman’s first contributions came in the defense industry. In 1968 the U.S. Navy’s Poseidon strategic missile was experiencing unpredictable wire bond reliability problems. The missile contained thousands of small aluminum wire electrical connections, and if one wire failed, the entire device/system could fail. Harman investigated this problem with a goal of improving ultrasonic wire bonding and the ability to evaluate its reliability. He developed a 60 to 120 kHz floating-cone capacitor microphone system to plot the ultrasonic vibration modes of bonding tools. It was found that aspects of the tools, such as the heat produced by lights used to aid the operator’s vision, could cause the highly sensitive bond setups to move out of specification, and that vibration from the bonding machines themselves could also cause unreliable bonds. The results of this work were applied to improve process control and measurement methods and yield a better understanding of other problems in the ultrasonic bonding machines/processes.

Harman started the ASTM F-01.07 committee in 1971 to standardize wire bond testing methods and was responsible for updating these standards in 2006. He also wrote the first version of the nondestructive bond pull test used for MIL-STD-833, and his 1974 paper, “A Metallurgical Basis for the Non-Destructive Bond Pull-Test,” stands alone as the statistical and metallurgical understanding of that test method. The nondestructive bond pull test is currently required for critical space parts used by NASA.

An IEEE Life Fellow, he holds four patents, and his numerous awards include the IEEE Centennial Medal (1984), IEEE Third Millennium Medal (2000), Outstanding Contributions Award [David Feldman Award] (1992), IEEE CPMT Outstanding Sustained Technical Contributions Award (2001), and the U.S. Department of Commerce/National Institute of Standards and Technology (NIST) Silver (1973) and Gold (1979) medals. Harman received a bachelor’s of science from Virginia Polytechnic Institute in 1949 and a master’s of science from the University of Maryland in 1959. He was a research fellow at the University of Reading (UK) in 1962-1963. He is a retired NIST Fellow, Scientist Emeritus, and consultant. [ieee.org]

Attleboro, MA—David Barnum is now general manager of Sensata Technologies Inc.’s worldwide Interconnection business. David brings 25 years of interconnection experience in general management, sales, marketing and engineering to this role. He has held various interconnection-related positions at Wang Labs, Burndy Corp., FCI, Augat Inc., Insilco Technologies, and Paricon Technologies. [sensata.com]

Irvine, CA—In a move designed to further expand the company’s market and sales leadership, Henkel Corp. has selected Jim Wise to direct the global sales effort for its electronics assembly business.
With over 23 years of chemical industry experience, the last 20 of which have been spent with Henkel businesses, Wise brings unique perspective and expertise to his new role. Providing a rare combination of both scientific understanding and management skill, Wise’s background includes positions in chemistry R&D, technical service, applications, manufacturing, sales and new business development. Wise formerly held top-level positions with Nacan, Acheson and Emerson & Cuming and was an asset gained through Henkel’s acquisition of National Starch and Chemical’s Adhesives and Electronics Materials business.

Wise has several business development priorities, the first of which is to address current and emerging customer requirements, delivering robust, yet cost-effective materials solutions that enable competitiveness for today’s and tomorrow’s assembly technologies. In addition, effectively communicating the breadth of the organization to customers is top on Wise’s list, as Henkel now successfully delivers materials solutions and an unmatched depth of knowledge for numerous product classes that include solder materials, conductive adhesives, circuit board protection materials, inks and coatings, underfills and thermally conductive materials, just to name a few.

While the product range is arguably impressive, it’s the company’s innovation, technology-enabling capabilities and low-risk partnership proposition that truly set Henkel apart competitively. “We bring expertise and advanced materials to the table that enable our customers to develop products or technologies that would not otherwise be achievable, making Henkel a key supplier and partner,” explains Wise. “Henkel offers more, as we don’t simply just supply a product, but a product backed by a highly skilled technical staff, a robust supply chain, top-notch customer support and know-how that allows our customers to create differentiable products or technologies and bring them to market faster. That’s what Henkel’s innovation commitment is all about and it’s a promise that we are delivering on consistently.”

A native of Canada, Wise is a graduate of McMaster University in Hamilton Ontario, Canada, where he received a Bachelors of Science in Chemistry, minored in Physics and Mathematics and graduated with honors. As leader of Henkel’s global sales initiatives, Wise will be based in the company’s Billerica, Massachusetts facility and will report to Henkel’s electronics assembly group Senior Vice-President and General Manager, Joseph DeBiase. [henkel.com/electronics]