An Independent Journal Dedicated to the Advancement of Chip - Scale Electronics July - August 2000 Email the editor

Flip-chip and chip-scale packaging come from very separate worlds, each with its own technological base. As the two converge in the cauldron of wafer-level packaging, it is becoming difficult to distinguish between them. I am often asked whether flip-chip and wafer-level packaging are the same. Some per-spective is helpful in answering the question. Flip-chip has been used interchangeably with the IBM C4 Process (Controlled Collapse Chip Contact), which is the high-lead solder ball used to connect the C4 chip to its substrate.

By Dr. Tom Di Stefano Contributing Editor

High-lead solder was used to relieve thermal stress and to provide a reliable contact between chip and substrate. C4 chips were intended for use in modules with low expansion substrates that minimize thermally generated stresses. These modules were often hermetically sealed to protect bare chips from the environment.

Vertically integrated companies use various flip chips in high-end computing, automotive and consumer products specifically designed for the requirement.

Standardization is unnecessary in vertically integrated applications where assembly, burn-in and test are engineered for the specific product. These flip chips can in no way be considered wafer-level packages, but rather are bare chips that are finished into packaged ICs by the manufacturer.

IBM Yasu began a significant departure from flip-chip orthodoxy with the introduction of underfill to improve the reliability of flip chips attached directly to memory modules.

Underfill encapsulates the chip and protects it from the environment. It also relieves stress by joining the chip to its substrate forming a bi-metallic strip that can flex in response to differential thermal expansion. Thus began a movement to adapt flip-chip for use as an SMT component and to minimize the quirky problems of designing for underfill.

Graphic shows the convergence of flip-chip and chip-scale packaging at the wafer level.

In converging toward a package that is SMT compatible, a range of technologies is being developed to solve problems of solder reliability and to protect the chip against handling and corrosion.

Posts, springs, stacked solder balls, flexible balls, low-temperature solder, conductive organic materials and many other approaches are being developed to provide reliable electrical connection to the chip. Successful solutions should provide acceptable reliability, even when assembled to a PWB without underfill.

With the MicroSMT introduced by National Semiconductor Corp. and with ICs from Dallas Semiconductor, we are beginning to see wafer-level packaging reach the market. On a broad front, flip chips are being dressed up and adapted for use as wafer-level packaged ICs.

While flip-chip-based solutions are moving toward providing a complete SMT package, chip-scale packaging is moving toward production at the wafer level to reduce cost.

Wafer-level production is a natural progression to processing more and more chip-scale packages in an array. Beyond cost reduction, chip-scale packaging is driven toward wafer-level production by advantages in logistics, burn-in, test and IC performance.

Convergence

In this convergence of technologies, we need a touchstone to separate the sheep from the goats.

The market expects wafer-level packaged ICs to satisfy certain requirements, including reliability. The package must allow assembly on a conventional SMT line without under-fill. It must be fully tested and protected against handling damage and corrosion. And it should meet industry-accepted standards.