An Independent Journal Dedicated to the Advancement of Chip - Scale Electronics July - August 2000 Email the editor

By David Francis and Linda Jardine, Contributing Editors Patent Number:6,013,948 Assignee: Micron Technology, Inc. Inventors:Akram et al. Title:Stackable Chip-Scale Semiconductor Package with Mating Contacts on Opposed Surfaces

This stackable CSP uses silicon as the substrate and is formed using various process steps to become a package carrier for stacking memory chips.

Figure 1. shows the fabrication of a single substrate, but all processing is performed at the wafer level.

The through holes are formed by laser drilling holes through a 28-mil thick silicon wafer. The entry hole diameter is slightly larger than the output hole diameter, although the difference is only a few percent. The laser wavelength can be a standard IR or green (1064nm-532nm). Figure 1. Hole and Cavity Formation

Etching

The etching step is generally a two-stage process to etch the die and wire bond cavities. Prior to etching, a cleaning solution is employed to remove any existing native oxide layers.

A hard mask material such as Si3N4 is deposited on the surface and patterned to form the open areas. The cavities are aniso-tropically etched using a solution of KOH and tretra-methyl ammonium hydroxide (TMAH). The slope of the walls formed by etching is 54o.

After the first etch, the masks are stripped and a second set of masks are applied and patterned to expose the cavities for final etching.

After the cavities are formed, the masks are removed and a suitable insulating layer is formed over all exposed silicon. This layer can be SiO2, Si3N4 or polyimide. This is shown in Figure 2.

The through-holes can be filled in a variety of ways with materials ranging from solder to conductive polymers. The conductive material can be applied by screen or stencil printing, dispensing or other methods. Figure 2. Insulating and Metallizing Substrate

Metallization

Suitable metallization layers are then deposited on the front and back surfaces of the wafer. These layers are then patterned to form the topside contacts, as well as the trace connections from the wire bond cavity out to the outer contacts on the bottom side of the substrate.

Various metallization schemes can be used. If solder balls are employed, the metallization must be solderable. Another requirement is that the metallization layer in the wire bond cavity be wire bondable.

In assembling this CSP, the memory die is attached face down using a suitable adhesive. The die is sealed in this cavity by applying a suitable encapsulating resin around the perimeter of the die bond cavity.

After wire bonding the same or a similar encapsulating resin is applied to the wire bond cavity.

Solder balls can be attached to the outside pads by laser reflow, welding or with a conductive adhesive.

While solder balls may be used, the connection between the CSP and the PWB or to other CSPs can be by means of any suitable process. Bumps can be formed by plating or with a wire bonder.

The memory die placed in these CSP packages can be KGD that have been previously tested and burned-in.