Current Issue An Independent Journal Dedicated to the Advancement of Chip - Scale Electronics May - June 2001 Email the editor

Edward Combs Edward G. Combs, Vice President of Engineering at ASAT, Fremont, Calif., joined the company in 1987 and previously served as Executive Vice President of Customer Engineering. From 1985 until he joined ASAT, Mr. Combs was Vice President of Sales and Marketing at Swire Technologies (since absorbed by Hana Semiconductor). Earlier, he was Operations Manager at Amkor. Mr. Combs attended San Diego State University and holds several patents in semiconductor packaging. [ed_combs@asat.com]

Q Are we likely to see a period of higher than normal consolidation of IC packaging foundries as a result of the slowdown?

A Many of the smaller packaging foundries are experiencing a larger percentage cutback than some of the larger companies that can leverage their assembly volumes. This may influence the decision of the smaller foundries to consolidate, either with other smaller companies or with some of the larger firms.

If the downturn continues, we may see more concerted efforts to consolidate for competitive reasons. I cannot speak for other packaging foundries, but at ASAT, we are always looking for opportunities to expand our business. A downturn in and of itself is not a reason to consolidate. ASAT will entertain any merger or acquisition opportunity, any time, if it is consistent with our strategic plans.

Q Will conventional packaging foundries be able to handle wafer-level packaging or will this business go largely to specialty firms?

A Wafer-level packaging is now starting to come into its own with the explosion of flip-chip requirements for high-speed applications. Conventional packaging foundries will have to address these requirements if they want to continue to compete in the high speed and RF market places.

In the near future, wafer-level packaging will become another "standard" packaging format, and the larger packaging foundries will put the necessary equipment and processes in place. This new packaging technology is a logical extension of existing array packaging. Those foundries who want to remain in the forefront of technology must adapt to the newest packaging needs. With device speeds continuing to increase, and board space continuing to decrease, the present "niche" market for wafer-level packaging will probably soon become mainstream.

As wafer-level packaging gains momentum and becomes a reality, it may well be absorbed into the foundry, since this is a batch process requiring some redistribution, although it's handled at the wafer-level.

Q Will packaging foundries be split between those that can handle wafer-level and/or high density, area-array packaging and those that will handle only plain "vanilla" surface mount formats?

In most cases, packaging foundries are already "split" into categories of "vanilla" products and high-density, area-array packages. That probably will not change.

Wafer-level packaging will require an entirely different infrastructure and manufacturing expertise compared to wirebond-based assembly. The cost of installing this new infrastructure may be easier for those foundries who already have high-density packaging systems in place.

There is also a considerable investment to consider for wafer-level packaging. This factor may limit companies who elect to get into this new field of assembly. As the densities and integration get tighter, the PWB or substrate maker will encounter the problems faced by the packaging foundries today.

Multichip modules and systems-in-a-package, currently the realm of the backend subcontractor, may be integrated into the EMS (electronic manufacturing services) companies. In turn, these vendors may merge with wafer-level packaging providers.

Q Is the cost of entry becoming higher for packaging foundries?

A I don't think there is any question that the cost of both capital equipment and facilities is continuing to escalate, and I don't see that trend turning around.

With the geometries of the wafer fabs continuing to shrink, the need for higher accuracy in the assembly arena is becoming very critical. This includes both wirebonded and flip-chip devices.

To compete in the high-end market, both technologies must be available-which increases the cost of the equipment required for the factory.

Packaging foundries are not highly leveraged. They are paid per-device and invest incrementally in capacity. Therefore, the cost of entry when viewed from a capacity perspective is relatively small, especially when compared to a front-end foundry.

By running high volumes of certain packages used by multiple chip makers, the packaging foundries' overall costs are lower, and the reliability and quality often higher.

Recently, business models have started to evolve with packaging foundries becoming technology partners in packaging and test, as opposed to being only cost-based.

Q China has recently become a favorite location for IC assembly. To what degree will that continue?

A China offers many advantages that are difficult to duplicate elsewhere, and I believe the trend to locate factories in China will continue.

The country offers a very well educated population from which to draw, an infrastructure that is fast becoming conducive to semiconductor manufacturing, and the cost of labor is definitely attractive.

China is also an extremely large consumer nation and the internal consumption of semiconductors is rising exponentially. This "built-in" market makes assembly in China most attractive for expansion.

China is not a "bit player." It is the biggest player in the world, and the future premium location for IC assembly may well be in China. Most IC assembly companies are Asian, even though they may be incorporated in the U.S. and managed by American executives.

Q Is the "new elite" in packaging foundries going to be those that offer final RF test vs. those that don't?

A I believe RF testing is becoming a necessity rather than an exception because of the increasing speed of systems and because of the proliferation of wireless products.

If the foundry does not offer RF capabilities, they will be "left in the dust." Full turnkey service is the wave of the future. Without test, we will not be able to satisfy the customer's needs.

Not only will final test be required, but also wafer probe through packing will be the blueprint of the future for foundries. Those who do not embrace this full service concept will most likely not be as successful as those that do.

Packaging is an integral part of the chip's functionality; therefore an integrated packaging and testing service is required for yield management and improvement. Test programs should be developed at chip design time. This program development is particularly important for RF devices, where the location of the chip in the cavity or the path or loop of the bonding (or the size of the solder ball) may impact final package performance.