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Current Issue
The International Reference for Chip-Scale Electronics, Flip-Chip Technology, Optoelectronic Interconnection and Wafer-Level Packaging
May - June 2002

Thin, Wafer-Level Package Is Made Without Damaging Die
David Francis and Linda Jardine
Contributing Editors

PATENT NUMBER:

6,338,980

ASSIGNEE:

Citizen Watch Co.Ltd.

INVENTOR:

Tetsuo Satoh

TITLE:

Method for Manufacturing Chip-Scale Package and Manufacturing IC Chip

This well-written patent describes the manufacture of a wafer-level package (WLP) that is very thin and which can easily be handled without damage. What is more significant is that the thinning process does not damage the die.

Prior Art

In one prior-art example, a partial groove was sawn and filled with resin. When diced, the sidewall was part resin and part silicon. While an improvement, it was still possible to damage the silicon by improper handling.

In a second example, the resin filled the entire side of the die, but it was not possible to thin the die. In this process, the die were handled individually, which lowered productivity.

The Invention

The wafer is bumped like a conventional flip-chip wafer. A passivation layer is applied, followed by the deposition of a suitable under-bump metallization (UBM). Eutectic solder is suggested for the bump material, although gold can also be used. The UBM is chrome and copper.

This patent should be good news for tape suppliers. The wafer goes through three taping operations.

The first tape is applied to the back surface of the wafer so that it can be sawn partway through.

Wafer thickness is typically between 600 and 700 microns. The depth of the saw cut is slightly more than the desired final thickness of the die. If the desired thickness is 100 microns, a cut depth of 125-150 microns is made.

Several spin-on applications of resin are used.A low-viscosity resin can be employed to fill the channel between die and this can be followed by a high viscosity resin as the top coating. Multiple applications may be required.

The resin can even flow over and cover the solder bumps. After curing, the resin coating over the solder bumps is removed using an ashing process.

Next, a front-side tape is applied so that the wafer can be thinned by grinding.

Tape Is Easily Removed

The first backside tape is removed by exposing the tape to UV radiation. This reduces the adhesion so that it can be easily removed.

The back side of the wafer is ground to remove all of the undesired silicon and expose the cured resin between each die. A third tape is then applied to the backside of the wafer (the side that has just been ground).

The tape on the front side covering the bumps is then removed. The final step is to saw the wafer into individual devices.

The graphic shows how a thin, strong wafer-level package is fabricated using the patented process.

Summary

This patent discusses a process that results in a very thin, bumped package able to withstand normal handling without damage to the die, because the sides are fully protected by resin.

The solder bumps are protected by resin as is the front of the wafer so that the resulting package is environmentally robust. The productivity of this process is very high since the steps are all performed at the wafer level.

The thinning yield is greatly enhanced. A problem with thinning die to thicknesses down to 100 microns and below is that the grinding induces edge cracks that propagate through the die. This process apparently eliminates that problem.

International Interconnection Intelligence is a market and technology research company specializing in the semiconductor packaging and interconnection areas. Contact David Francis or Linda Jardine by e-mail at iii1@ix.netcom.com or by phone at 650.728.5270. [iii1.com]

 
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