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By Dr. Se-Young Jang,Samsung Electronics Co. Ltd., Seoul, Korea, and Heinz Gloor, Unaxis Semiconductors, Trübbach, Switzerland
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| UBM interfacial interactions have been largely overlooked by the lead-free community, although many failures can and do occur at the interface.
This article provides insights on these reactions and discusses how the use of lead-free solders can improve
flip-chip reliability. |
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In today's electronics packaging world, flip chip is a key process for reducing package size, improving electrical performance and providing multi-chip packaging solutions for leading-edge formats, such as system-in-package (SiP).
Consider that some area-array flip chips contain more than 1000 I/O per chip-a number that is dramatically increasing.
The Lead-Free Movement
One notable flip-chip challenge is the "lead-free" movement. Major OEMs, including IBM and Sony, plan to buy lead-free parts and products starting in mid-year. Flip-chip processes, even though they use only very small amounts of lead, are not exempt from regulations.
Au, Cu, or electroless Ni bumps with ACF/NCP (Anisotropic Conductive Film/ Non-Conductive Paste) are ways to realize lead-free flip-chip interconnections. Reliable ACF/NCP methods, however, require very well-defined chip and substrate surface conditions because physically bonded interconnects are very sensitive to adhesion between polymer layers.
To date, chemical bonding by reflowing solder bumps is accepted as the preferred interconnect for IC packaging, because of its robust character.
Stencil Printing and Electroplating
In wafer-level solder bumping, two process categories, solder-paste stencil printing and electroplating, are dominant.
Stencil printing works for small ball sizes and low cost bumping. With solder pastes, however, a mixture of solder particles and flux may experience significant volume changes during the solder reflow process. Typically, larger spaces between solder bumps, usually measuring >150µm, are necessary for the process.
Electroplated bumping meets the fine-pitch requirements and cost effectiveness for high-volume production. Many in-house bumping lines and bumping service providers use electroplating for solder bumping in mass production. Switching electroplated solder materials and/or UBM is not simple because there are technical issues with plating prominent binary and ternary lead-free solder alloys. Major electrolyte providers and plating equipment companies are addressing this issue.
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| Figure 1. Schematic structure of flip-chip interconnection |
Figure 2. One example of flip-chip failure (UBM/solder interface crack) |
Underbump Metallization
UBM employs several metal layers beneath solder bumps and is a reliable method for making flip-chip interconnections. Figure 1 shows cross-sectional flip-chip and UBM structures; Figure 2 illustrates a flip-chip solder failure. In many cases, flip-chip failures appear in UBM neighboring sites such as chip/UBM and UBM/ solder interfaces.
Understanding the interface reactions between UBM and solder and further controlling them to improve flip-chip reliability are important tasks. Therefore, why not use conventional UBM for eutectic Pb/63Sn for lead-free solder bumps?
We conducted extensive investigations of several different UBMs, applied with a batch sputtering system. We tested these with both leaded and lead-free solder bumps (Figure 3). We found with NiV/Cu UBM, IMC spalling is not observed with either solder.
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| Figure 3. SEM cross-sectional images of eutectic Pb/63Sn and Sn/3.5Ag solder bumps on different UBM systems after 20 min reflow at 210°C for Pb/Sn and 250°C for Sn/Ag. Lead-free Sn/3.5Ag shows more aggressive reaction with UBM than eutectic PB/63Sn. |
Figure 4. Cross-sectional TEM bright field image of the interface between NiV/Cu UBM and Sn/3.5Ag solder bump after 5 min reflow at 250°C |
The image in Figure 4 is a cross-sectional TEM of NiV/Cu UBM and Sn/3.5Ag solder. It clearly shows that an unreacted NiV layer still exists underneath the reacted Cu-Sn IMC layer. The most plausible explanation for the lack of IMC spalling in thin NiV/Cu UBM is that underlying NiV layers provide continuing IMC growth sites even after total Cu layer consumption slows IMC growth rates.
Extreme multiple reflows (over 15), however, will result in total UBM consumption as well as bump delamination.
Sputtered Ti(W)/Cu (or Ni)/ Electroplated Ni UBM
In general, Ni has a slower IMC growth rate than Cu with Sn-containing solder. Therefore, UBM systems using an Ni final layer are preferred for lead-free solder bumps to restrict excessive IMC growth.
An interesting phenomenon occurs with Ni UBM and lead-free solder: Even though a very small amount of Cu is contained in the lead-free material (such as 0.5 ~ 1 wt.% Cu), the IMC phase formed between Ni and solder interface is normally Cu, Ni6Sn5, not Ni3Sn4.* This occurs because of the lower free energy at formation of Cu, Ni6Sn5 than Ni3Sn4.
As a result, there is a lower consumption of Ni UBM because IMC growth consumes Cu in the solder first, then consumes Ni UBM. When tested, Sn/3.5Ag shows rapid Ni UBM consumption compared to Sn/0.7Cu and Sn/3.7Ag/0.5Cu. This suggests that Ni UBM consumption rate is dramatically decreased by adding a small amount of Cu to the solder bumps.
One concern about using electroplated Ni UBM is Ni normally has higher internal stress than other metal layers and could induce chip cratering or cracking.
The Options
There are two main options in selecting an UBM system for lead-free bumping. One can still employ conventional UBMs such as sputtered TiW/Cu/electroplated Cu and sputtered Al/NiV/Cu combinations. Significant restrictions, however, on subsequent reflows are required to avoid excessive IMC growth.
The second approach uses low-stress electroplated Ni on top of sputtered TiW/Cu, TiW/Ni or Cr/Cr-Cu/Cu. Some companies use a stress buffer polymer layer between UBMs and chip pads to reduce stress. To introduce new UBM systems, intensive practical as well as fundamental studies are required.
Other Observations
It is very important to select an appropriate PWB-finish metallization. For example, when the PWB surface finish is Cu OSP, Cu-rich IMC growth occurs at the Ni UBM and solder interface, even though both UBM and solder did not contain Cu.
The Cu in a PWB surface finish diffuses through solder bumps and forms Cu-rich Cu-Ni-Sn IMCs on chip-side UBMs. This type of IMC growth rate is very high and is detrimental to package reliability.
Therefore, the metallurgical design of flip-chip interconnects (chip-side UBM, solder bump, PWB surface finish) should be integrated for successful implementation of lead-free flip-chip applications.
A flexible batch sputtering system simplifies implementing a wide variety of UBM applications at the needed compositions.
Reference
* K. Zeng and K.N. Tu, "Six Cases of Reliability Study of Lead-Free Solder Joints in Electronic Packaging Technology," Materials Science Engineering, p. 55, 2002.
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Dr. Jang is a senior engineer at the Micro-Joining Lab, Mechatronics Center, Samsung Electronics Co. She received a doctorate in materials science and engineering from the Korea Advanced Institute of Science and Technology (KAIST) in Taejon. She is currently a visiting researcher at the Fraunhofer Institute, Berlin, Germany.
Mr. Gloor is product manager, sputtering systems for Unaxis Semiconductors, Trübbach, Switzerland. He earned a mechanical engineering degree from the Technical University Neu Technikum Buchs in Switzerland. He also received an economics engineering degree from the University of Applied Sciences in Lichtenstein. [heinz.gloor@unaxis.com]
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