May 1998
eMail the Editor
Chip-Scale Packages for Center-Pad Memory Devices
Two variations of a chip-scale package, one employing tapeless lead-on-chip (LOC), the other using a flexible substrate, have been developed for center-pad memory devices.
By Masuzumi Amagai, Texas Instruments, 0ita, Japan
The dramatic increase in the number of devices and functionality of the latest ULSI designs has resulted in increasing chip size. Concurrently, to achieve higher circuit board component densities package dimensions have been shrinking.
Figure 1. Chip-scale package with LOC design
One of the best solutions is solder-bumped flip-chip on board (FCOB), also called direct chip attach (DCA). However, because of the current inability of the infrastructure to supply the solder-bumped, known-good die (KGD), and the corresponding fine-line and fine-spacing printed circuit boards, most of the industry is still working on these issues.
Meanwhile, chip-scale packaging (CSP) has emerged. It is currently being used for SRAMs, DRAMs, flash memories, and low-pincount ASICs and microprocessors. As costs to produce CSPs decline, they will be adopted for increasingly higher pincounts. Currently, most CSPs have been designed for peripheral-pad devices„not for center-pad devices.
To meet the design criteria for center-pad devices, Texas Instruments developed new"memory chip-scale packages" (MCSP). These CSPs replace small outline, J-lead (SO)) and thin, small outline (TSOP) packages which are widely used for center-pad devices, such as DRAMs.
Figure 2. Chip-scale package with flexible substrate