Solving the CSP Test Challenge

Let's face it. IC test is the toughest, most complex task in semiconductor production. Certainly both wafer fabrication and packaging aspects of chip-making challenge and sometimes baffles cadres of engineers. Still, for my money, test is the real puzzler.

Remember, at this stage of the process, we're not making anything, but we are spending money to prove we made it right. Perhaps, more than anything else, test is an auditing process that seldom tolerates even a miserly-few mistakes. Then, too, the cost of test, particularly from an equipment standpoint, is perhaps higher than any other capital machinery from wafer dicing forward.

You can easily add a half dozen or more new„and very high speed lead bonders for the cost of a rather small, albeit powerful ATE system.

As you'll read in this month's test articles, the emphasis for CSPs must be on streamlining the backend process. The test process itself remains rather straightforward. It's the handling and the transport of the packaged devices that humbles even the wisest among the test fraternity.

Author Jack Kessler works for Amkor Electronics Inc., the largest packaging foundry in the world„bar none. As you might imagine, Amkor's parent, Anam Industries, performs a substantial amount of test at multiple locations.

"The separation of test physically and culturally, "observes Jack," has resulted in some cumbersome, very expensive and time-consuming solutions." Jack is telling us what much of the industry is only now beginning to accept,"Singulating parts prior to testing is counterproductive."

Need more proof? Jack's in good company. Paul Emmett, ChipPAC (who once worked for Jack at Amkor), agrees: "The real challenge is in the handling of the packages during the test process."

Dr. Sassan Raissi, this issue's interview expert, contends that the know-how and technology to address CSP's test and handling demands exist today. As soon as test/handling equipment users step up to the plate with their purchase orders and a true spirit of cooperation, the equipment makers will respond in kind. It boils down to the old chestnut,"There is no such thing as a free lunch." You can help us, the infrastructure and your colleagues by letting us know how you handle your CSP test challenges. And mark May 5-7 on your calendar. Those are the dates for Chip Scale International, the premier event for the chip-scale electronics community. I hope to see you there.

Cordially,

Ron Iscoff
Editor