Stepped Interposer Chip-Scale Package

By David Francis and Linda Jardine
International Interconnection Intelligence Inc., Montara, Calif.

Patent number: 5,714,800 Motorola
Inventor: patrick f. thompson
Title:Integrated circuit assembly having a stepped interposer and method

The packaging approach illustrated in Figure 1 shows the design of a stepped interposer and how its design eliminates the drawbacks of the prior art.

The stepped interposer is applied to the center area of the IC with a suitable compliant adhesive. The adhesive layer can be a continuous one or it may consist of a series of dots. This layer provides both physical and electrical isolation for the IC.

The patent does not provide much detail on the construction details of the interposer except that it can be of any organic or inorganic material.

Various configurations of the interposer are shown in Figures 2 and 3. In Figure 2, tape automated bonding can be used to make the connection between the IC pad and the interposer step.

In Figure 3, there is a step in the interposer that could be formed by some type of coining operation. The coining operation drops the level of the outer pads below the surface of the external pads so that wire bonds can be made and protected by the top surface.

Figure 2. TAB is employed to make the connection between the IC pad and the interposer step.

Figure 3. A step in the interposer has been formed by a coining operation.

Figure 4. The stepped interposer can be formed by more than one layer and/or material. Through holes can be made for connecting the various layers.

The devices can be encapsulated by a variety of means. The mold design is much simpler and it is much easier to prevent mold resin from getting on the external pads. Not only are the wire bonds protected by the encapsulating resin, but the top surface of the interposer continues to provide additional protection.

Another benefit of this design occurs when a liquid encapsulant is used. A requirement for using liquid encapsulant is to provide barriers for controlling and limiting its flow. With the approach described in this patent, the interposer provides that barrier.

The height of the interposer step is a key parameter. It must be sufficient to protect the highest wire bonds. It is suggested that the interposer height be at least 0.1 mm above the height of the wire bonds to provide the desired degree of protection.

Figure 4 illustrates a variation of the basic interposer design. The interposer can be made of more than one layer. For example, the layer nearest the IC could be the customizing layer, which is different for each IC. The top layer could have a standard footprint with pads on 1.0-, 0.75- or 0.5-mm centers.

The connection between layers is not clearly specified. In one case, throughhole connections can be made by drilling though all the layers and then plating. Alternatively, the top layer can be attached to the lower using some type of conductive adhesive.

This stepped interposer CSP design can be applied at the wafer level. The adhesive dielectric between the interposer and the IC can be easily applied by screen printing. The interposer is applied at the wafer level and then cured. Wires are bonded to make the interconnection and then encapsulated. Sawing separates the individual die. Solder balls can be attached after encapsulation or bumps can be provided on the next-level substrate.

The strengths of this design are the protection offered to the wire bonds before and after encapsulation and the relative simplicity of the encapsulation process. This approach will most likely eliminate the need for a die bonder, but will continue to make use of wire bonders. The die design retains the standard perimeter pad arrangement.

The major drawback to this CSP design is that the die must be large enough to have an open area sufficient to handle the number of I/O at the desired pitch. This is more likely to be a "system on a chip" and memory-size die than conventional logic and smaller functional devices.

International Interconnect Intelligence is a market and technology research company specializing in the semiconductor packaging and interconnection area. Contact the authors at iii1@ix.netcom.com or phone 650.728.5270.