May 1998
eMail the Editor
The Mysteries of JEDEC: Issues of BGA Standardization
By James Hayward, Advanced Micro Devices, Sunnyvale, Calif:
The appearance of any new assembly or packaging technology is frequently accompanied by a demand for the development of standards. The common thought is that standardization will encourage the development of an appropriate infrastructure and thereby hasten the acceptance and implementation of the new technology.Collective Decision
Standardization does not, of course, happen by magic when called forth, but is a collective decision by the industry to limit, in some way, the inevitable range of choices allowed by the new technology.The process by which this limitation of allowable options is performed is often seen as a mystery by those not directly involved„even if in hindsight the results may appear to have been inevitable. The range of issues which must be considered may be large and the mechanism is slow, so that infrastructure and standards, more often than not, mature in parallel, providing input to the other over time.
In my discussion, I will attempt to explain the mechanism by which package standards are generated and explore some of the issues which were considered during the development of the current BGA standards. The process is ongoing, so this will be far from the final word possible on the subject.
In the United States, the primary organization concerned with standards for the semiconductor industry is the Joint Electron Device Engineering Council (JEDEC) which is part of the Electronic Industries Association (EIA).
JEDEC has been functioning within the EIA since 1958 and currently consists of 11 working committees overseen by the JEDEC Solid State Products Council (referred to hereafter as the JEDEC Council).
Membership on any of the JEDEC committees is open to companies with a manufacturing presence in the United States.
Working Groups
There are now some 300 member companies participating in JEDEC activities, although not all companies participate m a committees and the number of companies associated with each committee is not the same.The various committees are the working groups within JEDEC responsible for the development of standards documents under formal charters approved by the JEDEC Council. The scope of activity for each committee is clearly defined in order to avoid overlap of responsibilities and the confusion that would likely result. The differences in scope frequently require cooperation between the committees in order for them to complete their deliberations.
The JC- 11 committee is chartered with the standardization of a package's mechanical outline. It is one of the larger committees with 120 companies represented among the membership. The member companies represent semiconductor manufacturers, contract assemblers, OEMs, test equipment manufacturers and socket manufacturers, among others.
The documents which JC- 11 develops are published in JEDEC Publication 95 (JEP-95), Registered and Standard Outlinesfor Solid State and Related Products, and the related JEDEC Standard 95-1 (JESD 95-1), Design Requirements for Outlines of Solid State and Related Products. (Published for convenience together with JEP-95 as a single document compendium.)
These publications contain mechanical outlines of packages for discrete devices and integrated circuits and such auxiliary items as shipping tubes and trays (JEP-95), and design guides for formulating these outlines ( JESD 951). There are now over 500 numbered outlines in JEP-95 with several times that number of variations within the outline families. Such a large number of defined package types represent not only the broad range of JC-11 member companies, but a repository of the history of the development of the semiconductor industry since JEDEC's establishment.
JC-11 Procedures
The JC-11 committee, unlike other JEDEC committees, produces two types of documents: registered and standard outlines. Although in common thought the two types of outlines are not clearly distinguished, they differ in intent and in their development process.Registered outlines are intended to define newly-introduced packages or package families which are still in an immature state of development.
These outlines are developed within the JC-11 committee only and are subject to frequent change. The intent of the registered outlines is to document the industry's first thoughts on the design of the new outline and provide a baseline around which an appropriate infrastructure can develop.
As usage increases, the outline can be modified to reflect improvements, correct initial flaws, adjust dimensions and tolerances, etc., based on increasing knowledge of the problems encountered during implementation.
Registered outlines may be distinguished by the format of the outline number which will always be xO-xxx, e.g., MO129, TO-220 or CO-012. The approval procedure for registered outlines can be summarized in the following steps:
- Present outline proposal at JC-11 committee meeting and obtain approval for registration ballot;
- Prepare ballot and distribute to JC-11 membership for a vote;
- Present ballot results at JC-1l committee meeting (including resolution of any objections);
- Revise outline if necessary and repeat 2-3;
- If approved by a ballot vote, prepare outline for publication by JEDEC office.
Even if an outline has been published as a registration, any member company (or companies) may revisit the outline for revision following the same procedure. The rapidity with which a new outline is first developed or subsequently revised is dependent on the degree of acceptance of the proposal by the committee and the consequent number of ballot cycles needed to obtain the necessary approval.
Standard outlines require a similar, but more extended procedure for approval since they are intended to represent mature package technologies which will undergo little or no change once the standards have been published.
Standard outlines are distinguished also by the format of the outline number which will always be xS-xxx, e.g., MS-012, TS-004 or CS-006. For a document to be published as a JEDEC standard, the approval process must also include approval by the JEDEC Council. The approval procedure for registered outlines can summarized in the following steps:
- Present outline proposal at JC-11 committee meeting and obtain approval for standard ballot;
- Prepare ballot and distribute to JC-11 membership for a vote;
- Present ballot results at JC-11 committee meeting (including resolution of any objections);
- Revise outline if necessary and repeat 2-3;
- If approved by JC-11 ballot vote, prepare outline for ballot by JEDEC Council;
- Present ballot results at JEDEC Council meeting (including resolution of any objections);
- Revise outline if technical changes are necessary and repeat 2-6;
- If approved by Council ballot vote, prepare outline for publication by JEDEC office.
Additionally, since the Council places considerable weight on the results of the individual committee deliberations, documents submitted for standards approval will have achicvcd near unanimity in JC-11 before submission.
Since JEDEC has been accredited by ANSI as the source for U.S. national standards for the semiconductor industry, JEDEC package outline standards also have additional significance as national standards in discussions with international standardization organizations. This status does not apply to outline registrations.
Overall, the general procedure for developing a package outline standard for a new package technology implies proposing an outline registration, allowing the registered outline to pass through several revisions, then proposing a standard outline based on the matured registration.
In practice, most registrations do not become standards either because they lack the popular support necessary or fail to achieve maturity before being abandoned. Only the most significant package technology developments eventually rise from registration to full standard status.
The process described is performed by representatives of the member companies. Thus, any outline proposed to JC-11 must gather at least some degree of support in the industry sufficient to spur action by at least one of the members.
BGA Outline Development
The development of outlines for the various BGA package types illustrates the processes described above. This development has been ongoing for 6-7 years while the usage of BGA packages has been increasing.At the time of their introduction, BGA packages represented a radically different package format from thencurrent surface mount packaging. The only precedents among JEDEC outlines for packages with arrays of contacts were the PGA outlines developed during the mid-1980s.
The substitution of solder ball contacts, however, presented several new problems to be solved. In the early deliberations to define the BGA families, the effects of the outline decisions on many different aspects of how BGA packages would be used had to be considered.
Although the primary function of a JEDEC package outline is to define packages aufficiently to ensure interchangeability between manufacturers, and to give the user enough information to design products with the packages, it is also necessary to define packages which can be manufactured by suppliers. Thus, the interests of manufacturers of sockets, test handler equipment, assembly equipment, shipping mechanisms, et al., as well as those of the end user, have to be considered.
Reliability requirements are not included within the scope of JC-11 outlines, but the reliability of the defined package must be considered in the generation of the outlines. It is seldom possible to completely satisfy all of these requirements, so the standardization process is partly one of arbitrating the demands. The result in the best case allocates the compromises equitably over all parties.
Issues
The fundamental issues needed to begin defining the BGA package outlines were not unusual: Such items as body sizes, lead (ball) pitch, package thickness and lead (ball) count are common to any package format.The BGA package was introduced to JC-11 during the time that the committee was making the transition to outlines defined entirely in metric dimensions, so that would be the rule followed for this outline. The committee also made the decision to extrapolate from the few example packages developed by the sponsoring company and define a broad family of BGA packages in anticipation of future use.
The values assigned to the various outline dimensions would, thus, be algorithmically based rather than just reflecting the values tooled at the time. One of the keys to this extrapolation was the definition of the ball array pitch.
The initial proposal called for a 1.50 mm ball pitch and this was used to define a range of body sizes. For 1.50 mm pitch, body sizes were defined from 7.0 mm to 35.0 mm in 2.0 mm steps.
The selection of the 2.0 mm step in this progression meant that the maximum array size would increase by at least one for each increase in body size. Thus, for a square body size of 23 mm the array size would be 15x15, and for a square body size of 25 mm the array size would be 16x]6. The maximum array size was calculated for each body size based simply on the largest number of balls that could be contained on the body surface.
Significant Impact
Performing this calculation additionally required a definition of ball size and both size and positional tolerances, as well as size tolerances for the BGA body itself. The combination of the ball dimension and tolerances required careful consideration since the result would have a significant impact on BGA substrate layouts, PC board layouts, socket contact mechanisms and solder joint reliability.The initial ball diameter selected (0.75 mm nominal for 1.50 mm pitch) has remained unchanged since its inception, but several of the associated tolerances first chosen have been modified as additional information has been made available to the committee.
Pitch Reduction
Atter selecting the base family of packages at 1.50 mm pitch, the comn1ittee looked at pitch reduction as the method to increase the ball matrix size on any given BGA body size. Ultimately pitches of 1.27 mm and 1.0 mm were chosen.(Pitches less than 1.0 mm were considered, but were believed to be beyond the capability of package and board manufacturers at the time.) Appropriate ball dimensions were selected for these pitches and new array sizes calculated. Thus, three families of BGA packages were generated and formed the basis for the first issuance of the BGA registered outline, MO-151. This outline included only BGAs with square bodies, since there was no accepted method to define the body size progressions for rectangular BGAs.
One of the issues unresolved in MO-151 was the overall height of the package. Early on there were a number of BGA constructions making their first appearance including PC board-based, ceramic-based and tape-based versions and JC-11 had insufficient information to sort the special requirements based on construction or materials. So, MO-151 in this regard was viewed as a blanket outline which would encompass any configuration until additional requirements could be defined. This and other issues were to be addressed through the revision process. And, indeed, the original MO151 has been revised three times since first being published.
The revisions have included tolerance adjustments, addition of body sizes between 35 mm and 50 mm (in 2.5 mm steps reflecting the sizes of ceramic BGAs), the addition of body sizes below 15 mm in 1 mm steps (to provide greater variety in matrix size at the smaller pitches) and a second matrix size definition (to ensure a minimum ball-to-bodyedge clearance).
The publication of MO-151 and its revisions was hardly the end of the BGA standardization effort. Subsequent proposals to JC-11 led to publication of additional BGA registrations for the ceramic and tape-based version as well as column-grid, low-profile and rectangular variants.
And as experience with the BGA packages increased, it became possible to begin codifying the design algorithms into a section of JESD 951 as the basis for beginning the evolution of the BGA registrations into formal standard outlines.
The first version of the design standard was published as Section 14 of JESD 95-1 early in 1997 and the first BGA standard outline (for several rectangular packages) followed shortly thereafter. The BGA-related outlines presently published in JEP-95 include:
- MO-149: Square tape ball grid array packages (1.5 mm,1.27 mm and 1.0 mm pitch);
- MO-151: Square plastic ball grid array packages (1.5 mm, 1.27 mm and 1.0 mm pitch);
- MO-156: Square ceramic ball grid array packages (1.5 mm, 1.27 mm and 1.0 mm pitch);
- MO-157: Rectangular ceramic ball grid array packages (1.5 mm,1.27 mm and 1.0 mm pitch);
- MO-158: Square ceramic column grid array packages (1.5 mm,1.27 mm and 1.0 mm pitch);
- MO-159: Rectangular ceramic column grid array packages (1.5 mm,1.27 mm and 1.0 mm pitch);
- MO-163: Rectangular plastic ball grid array packages (Replaced by MS-028);
- MO-192: Low-profile square plastic ball grid array packages (1.5 mm,1.27 mm and 1.0 mm pitch);
- MS-028: Rectangular plastic ball grid array packages (1.5 mm, 1.27 mm and 1.0 mm pitch);
Feedback from experience is used to refine package documentation with the result that the industry is not straitjacketed by poorly conceived or overly restrictive standards. A good example of how this interaction works might he the development of BGA sockets. Since the design of ball cclntact mechanisms depends on the ball size specifications, estahlishing those dimensions early allowed socket manufacturers to begin designs and evaluate the results early as well.
The same situation pertained to tray manufacturers who needed definitions of body and matrix sizes in order to begin designs for shipping trays.
Shipping tray designs are, of course, of interest to manufacttlrers of test handlers and assembly equipment. Representatives from these companies all participate in JC-11, so issues raised during the design evaluations were important to the continuous improvement of the outline documents.
Global Discussions
Although interest in BGA packaging began in the U. S., the advantages of this package format were soon recognized throughout the world and standardization activities in Japan and Europe began shortly after those in the JEDEC. Functioning in JEDEC's role as the U. S. national standards organization, JC-11 engaged in global discussions on the development of the design standards through its interactions with the Electronic Industries Association of Japan (EIAJ) and the International Electrotechnical Commission (IEC).The goal of this activity is to achieve an international standard useful throughout the worldwide industry. Although no one can yet claim that this has been accomplished, major steps toward that goal have been taken.
This paper, originally presented at ITAP '98, has been edited for Chip Scale Review. It is copyright 1998, and is used by permission of SemiTech Inc., Neffs, Pa.
Mr. Hayward received a bachelor's degree in chemistry from Harvard University. He is a Senior Member of Technical Staff in the Manufacturing Services Group at Advanced Micro Devices (AMD) Sunnyvale, Calif. His responsibilities include new technology evaluation and the development of AMD's packaging strategy.
He has been the AMD member of the JEDEC JC-11 Committee since 1982 and was instrumental in developing the JEDEC outlines for PGA, TAB and BGA packages and participates in the current activity for CSP outlines. He also participates in the annual JEDEC/EIAJ meetings and task groups. Prior to joining AMD, he worked at Northrop Electronics, Dataproducts Corporation and Burroughs (now Unisys) Corporation. Contact him at 408.732-2400 or by e-mail at james. hayward@amd.com.