Chip-Scale Packaging Final Test: The Paradigm Shift Begins

The technology and materials employed for csps are driving the industry to new "package-independent" test-handling concepts which require no tooling, no sockets and no singulated parts handlers.

By Jack Kessler, Amkor Electronics Inc., Santa Clara, Calif.

The Paradigm Shift Begins the technology and materials employed for csps are driving the industry to new "package-independent" test-handling concepts which require no tooling, no sockets and no singulated parts handlers.

The advantages of the chip-scale package are its small size, speed and its ability to fit into places standard packaging cannot. However, because CSPs are "die size," they will continue to change size„in outside dimensions and thickness or both.

This will occur at every die shrink, or when the wafer backgrinding is thinner, the die has a smaller size or no solder balls are used. As long as the matrix and pitch of a product remain the same, the end user will be readily able to handle and place CSPs on PC boards. While we're on the subject of pitch, we are all aware of the "standards" imposed: 1.0, 0.8, 0.75, 0.65, 0.5, 0.4 mm, etc.

Test and test handling, unlike the majority of assembly processes, are not only package thickness and outer-dimension dependent, they are also pitch, ball diameter and height dependent. Moreover, they are ball material as well as die-type dependent. In addition, consider that test handlers are also carrier (tray or tube) dependent.

From a test-handling standpoint, the CSP is a challenge logistically, technically and financially.

Test Infrastructure
Test, for many reasons, has been separated from all other process flows in semiconductor manufacturing. Even wafer sort/test is traditionally handled on a "test floor," not in the fab, which prevents immediate and continuous feedback on process and yields.

This separation of test, physically and culturally, has resulted in some very cumbersome, expensive and time consuming solutions. These solutions, in turn, have resulted in additional costs, cycle time and reduced quality and productivity. The separation has included the separation of the packages from the leadframe adding even more problems.

With the advent of the CSP and the myriad of package sizes it allows, test is a major determining factor in the industry acceptance of the chip-scale package. Other factors include the constant change in size and a comparatively rapid design-to-market cycle time, none of which allow sufficient time for handler, socket or tray tooling.

Bottom line, if a part cannot be cost-effectively tested, then only device types with high average selling prices (ASP) can be used, and the package will not grow in popularity. To understand the impact better, let's examine the test flow and infrastructure for a standard memory product. This is an obvious place to start, since the bulk of initial products in the U.S., slated for CSPs, are memory products.

Figure 1. Standard memory devices flow. While this appears to be straightforward, the number of operations require from singulate to tape and reel is excessive.

Product Flow
Figure 1 depicts a flow that appears to be straightforward„at least for those familiar with today's assembly and test processes. The operations with a small, black triangle in the lower right corner are standard options for memory packages today. Note the number of operations from singulate to tape and reel.
If we add the necessary transfers to and from trays, we find conditions ideal for device and ball damage. In fact, the transport of singulated units inside the factory is the major cause of lead or package damage. In trays, the parts are in jeopardy from the time they are singulated until they are placed in tape and reel.

Note the number of times that parts are put into and taken out of trays from singulation to final shipping (Figures 1 and 4). All are potential sites for package or ball damage. Note also the number of operations from singulate to tape and reel operation. Now we add the infrastructure and equipment needed for test and burn-in, based on the flow outlined. Remember that package size (thickness and outer dimensions), ball pitch and diameter, ball array and its relation to the package edge affect each operation. The diagram in Figure 3 makes the total impact more obvious.

What is not readily apparent are the delays and costs of new tooling for sockets, handlers and trays and the potential for error and device damage. Good samples are needed prior to final tooling, which mean more delays. The smaller the package, the finer the pitch; the smaller the balls, the less forgiving the equipment can be. These requirements call for tighter tolerances, higher cost, longer delivery times and a smaller chance for standardization.

Figure 2. Memory flow using carriers: Note the number of times devices are placed in the remove from trays.

Paradigm Shift
The cost of continued separation and isolation of test from assembly, specifically with CSPs, will eventually force open the barriers to a better testing solution. In fact, packages like the 8-lead TSSOP package and 5-lead SOT-23 package are already making this shift away from singulated parts handling.

Starting Over
If we were able to start the assembly process over, it might occur to more people that singulating parts prior to testing is counterproductive. At present, we assemble packages in a leadframe or strip because it reduces cost, improves quality and eases handling as well as increasing capacity.

Figure 3.Equipment infrastructure. A variety of factors affectt each operation, incurring additional.

At the end of assembly, we singulate the packages and put them into carriers and inspect the devices. From that point on, time, money and quality are wasted in an attempt to get the packages back into a matrix or strip to aid in locating and handling parts. That is the purpose of the tube (strip format) and tray (matrix format).

The fact is all we really had to do was leave parts in either tube or tray, in the strip or leadframe, and avoid all the added costs and delay incurred by transferring them.

Why didn't this happen earlier? There are many reasons, from lack of test technology at assembly vendors to lack of assembly knowledge at test handler vendors, to the NIH (not invented here) syndrome.

Two obvious reasons make changing the test paradigm for CSPs more attractive than ever. The major ones involve the substrate and ball matrix, used in place of copper leadframes. The elimination of copper leadframes eliminates many assembly steps, such as trim and form, dambar and dejunk, and makes singulation a relatively easy task. The other essential factor is the small size, small pitch and low average selling price ASP of devices housed in CSPs.

Recalling the flow in Figure 2, let's examine what might happen if parts were not singulated before leaving the assembly area (Figure 4). Note the number of operations between singulation and tape and reel. Also note the lack of trays, multiple ball inspection, re-work, re-inspect or re-anything.

Some New Handling Concepts
To start over, we need a place to begin. Eliminating gravity feed handlers and pick and place handlers is a place to start. If we go back into the process and look at wafer probe, some ready concepts come to mind.

Figure 4.Strip format flows: Parts were not singulated before leaving the asembly area.

What if you could probe the CSP while it was still in a strip format? That would reduce the need for trays, sockets and tooling for different package sizes. Because the strip would remain constant in width, the tooling would then be affected by the pitch and ball location on the backside of the strip.

If we follow the process shown in Figure 5, the concept becomes a little more understandable. By selecting a wafer-shaped carrier, we can use a standard wafer prober and all of the features available for probing. To ensure accurate and solid mounting of the strip, we attach a strip of GelPak® (directly to the aluminum carrier, which holds the CSP strip of BGA packages, for example) in place. This also provides a safe, protective surface for the backside of the die. An added benefit is that the GelPak is reusable.

Figure 5. Package-independent handling of CSPs will reduce the number of processing steps, thereby reducing damage to devices and cost of test.

If we take the concept one step farther, it becomes apparent that this carrier provides a viable means of standard single, as well as multi-unit testing with a standard wafer prober.

The big payback results from obtaining a totally "package-independent" means of test handling with no tooling, no socket and no singulated parts handler.

Amkor Electronics is working with membrane contactor vendor, Micro- Module Systems, Cupertino, Calif., and custom prober vendor, AVISA Corp., Vacaville, Calif., in developing the package-independent concept. The goal is to develop a multisite, long-life contactor that is package independent and uses existing handling and probing systems.

The "probe head" is designed to mount over a prober or an offline or inline strip handler for CSP's. The prober will be modified for strip-to-strip and magazine load and unload after the process has been debugged and proven production worthy.

The initial concept utilizes proven hardware and allows magazine-to-magazine load and unload. Add wafer mapping and offline inking standards in today's wafer probing, and you have a very cost-effective means of package-independent handling and testing of CSPs.

Better yet, either a strip or a singulated device can be tested with this method, which means that for the cost of a contactor or probe, a new package size array or pitch can be readily tested. The prober aligns packages easily and the Gel-Pak will hold a single unit or a strip securely.

(The method of proving and providing interim volume testing is shown in Figure 6.)

The next obvious step is to eliminate the aluminum carrier and go directly to the strip in leadframe format. This provides an ideal means of handling CSPs in the same manner and with the same equipment used in the package assembly.

This prober concept, as well as the contactor hardware, will be incorporated into the strip tester. What will occur is not standardization, but consolidation resulting in reduced assembly and testing costs, utilizing proven technology for fast, accurate device location, as detailed in Figure 7.

Burn-In Using the Strip Format
For a moment, carry this concept of strip handling and membrane multi-site contacting to burn-in. The ability to test and burn-in using the same format and same membrane looks very attractive from the standpoint of both cost and and cycle time. This process is being evaluated by MicroModule Systems and AMP Inc. in an attempt to reduce burn-in costs to acceptable levels for certain CSPs.

With the parts in strip format in leadframe carriers, and loaded in magazines, the parts are very well protected and can be readily transported to the next station for marking, singulation, sorting and placing in pocketed tape. In fact, this brings up the possibility of shipping untested parts in leadframes in magazines to test floors anywhere, completely eliminating the need for trays or intermediate carriers.

Summary
It is rapidly becoming apparent„with the many new packages being tooled in record time using organic substrates„that something needs to be done at end-of-line. The cost of handlers, inspection and taping systems continues to soar. The existing need for kits, trays and sockets for each device type and each operation will become financially painful very rapidly, and will result in changing to a package-independent means of handling and testing packages.

The chip-scale package will force the industry to take a long, hard look at the traditional separation of test and assembly because new and smaller packages with low ASP die are driving the need for new and inexpensive package-independent ways to handle packages for testing.

The ideal solution appears to be the elimination of singulated handling until final placement in tape and reel. Amkor has initiated projects for strip testing„not only for CSPs, but also for low ASP, high volume packages. Successful completion of these projects is critical in meeting the demands of our customer base for less expensive testing, shorter cycle times and increased quality.

"Package-independent, pitch-dependent handling" is a phrase that will become the watchword for testing the new, smaller packages from the TSSOP to the µBGA package, flip chip and the next package generation.

Mr. Kessler is director of advanced test technology for Amkor Technology. His 23-plus years in the industry have been spent in all aspects of postfab manufacturing with an emphasis on test handlers and problems of singulated package handling. Before joining Amkor, he spent 15 years with National Semiconductor in both the United States and Japan. During that time, he established the Test and QA Group at NSC in Japan. He is now part of a team developing low-cost, post-assembly handling solutions. Contact him at 408.496.0303, fax 408.496.0392 or by e-mail at jkess@amkor.com.