May 1998
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Chip-Scale Packaging vs. Flip-Chip
By Mike Campbell, BPA Group Ltd.
Last year BPA Ltd., an international consulting company, undertook a major study to investigate the global commercial opportunities that exist in chip-scale packaging and flip-chip technology.The study, which is now complete, highlighted many significant commercial opportunities expected within the next five years. This article presents some of the findings from the study and presents a future view of the growth rate of these two emerging technologies.
The key feature of the BPA study was its methodology. All forecasts were developed by using a top-down methodology which took into consideration the forecasted growth of finished electronic systems and their expected usage of CSP and flip-chip technologies between 1996-2007.
Demand Exists
There are many factors which will determine how quickly CSPs are adopted, and there is little doubt in the industry that demand exists, particularly in the portable electronic systems market. Also, some devices in CSP packages are already being offered at lower prices because they are cheaper than TSOPs. Sony's flash memory chips in LOC-type CSP packages is one example .While these factors indicate that there will be a very rapid adoption of the CSP concept, remember that it will take significant time to establish the infrastructure that is needed and which entails a commitment by both the IC manufacturers themselves and their packaging houses.
This growth of the infrastructure is apart from the necessary work to research and develop, establish processes, confirm reliability, usability and manufacturing equipment. Equally vital is a ready availability of very high density PC boards and the necessary board assembly equipment and processes.
Figure 1 shows BPA's forecast for the use of flip chips between 1996 and 2007. Flip-chip technology in certain applications has been established for many years, mainly implemented by vertically integrated IC/systems houses such as IBM and Delco.
One of the basic problems inhibiting wider use has been the availability and the cost of chip bumping; costs of bumping, however, are dropping, and there are no more merchant suppliers that are likely to use this technology, as well as some very high volume requirements. One application we forecast flip chip will be adopted for is as a replacement for wirebonded die in smart cards.
There are a number of good technical reasons for this, and BPA is aware that there is a significant amount of effort being devoted to such a change.
Figure 2 shows BPA's forecast for the use of CSPs and NCSPs (near chip scale packages). It is BPA's opinion that even if true CSPs are cheaper, NCSP packages will still be required in the longer term for IC geometry downsizing, since many users will still want to buy the original size part with the same assembly footprint. Otherwise, they will be faced with having to redesign the entire circuit board, and„in some cases obtain end users' approval which may not be possible. At a minimum, this will be an expensive and time consuming process.
Figure 1. BPA's flip-chip forecast from 1996-2007
Supporters of NCSPs claim that, in many instances, these can be produced at a lower cost than true CSPs, and there is little doubt that in some cases this will be true, since materials will be cheaper and assembly simpler for NCSPs. However, it is BPA's view that as time goes on, and as the industry progresses down the learning curve, many of the material cost problems of true CSPs will be solved and they will be preferred over NCSP solutions.Nevertheless, there are good reasons to believe that these latter packages will find volume use in the short-to-medium term since the relatively small reduction in board area that arises from the use of true CSPs is not significant compared to the advantages that emerge from replacing current PQFPs and J QlPs with NCSPs.
Once a particular package is established, it is only likely to be substituted by a new one if there are very sign)ficant cost or technical reasons. ( Figure 3 illustrates the typical cost profile of an emerging technology compared to an existing one.)
Emerging Opportunities
CSPs and flip-chips will also be used to package discrete semiconductors„either individually or as multiple arrays of small signal diodes, transistors, or simple combinations„ with or without resistors/capacitors, all on one silicon substrate. Already, flip-chip technology is used for power devices and small signal discretes.While most of the above devices use the technologies developed for ICs, they are statistically reported as discrete devices. It was predicted that many of these devices would disappear as the level of IC integration increased. However, this has not happened, and the total number of small-signal diodes/transistors grew from 79 billion in 1992 to 121 billion in 1996, a CAGR of over 11.5%.
In 1996 there were over two discrete small-signal devices used for every IC2. In addition, over 28 billion power rectifiers, transistors, thyristors, etc., were consumed in 1996, over half of all ICs!
BPA also sees both CSP and flip-chip being used for passive component arrays constructed on silicon substrates, a trend which is already evident for improving electrical characteristics, reducing physical size and exploiting the very fine conductor patterns available from IC thin film technology.
While this article concentrates on CSPs and flip chip from an IC point of view, the additional use of flip chip and CSP technology, for "other" applications could at least double the opportunity for materials and equipment including:
- Subcontract CSP package assembly and flip-chip bumping
- CSP and flip-chip manufacturing equipment
- Materials required for CSP and flip-chip construction
- New, compatible high-density substrates
- Equipment and materials required to construct these new substrates
- Board level subcontract assembly
- CSP and flip-chip test and burn-in sockets and equipment
- Very high density board level test and diagnostic systems
- Board level repair equipment
Subcontract IC Assembly
The worldwide subcontract IC assembly industry currently accounts for over 50% of total IC packaging, although many major IC companies have their own packaging facilities, mainly where wages are low. There is an increasing level of onshore packaging using high levels of automation. The result is reduced work-in-progress, faster turn around time, reduced inventory and savings on transport costs.The subcontract industry can, over the longer term, expect to share a very high proportion of the CSP packaging business. For 1997, BPA has projected a total manufacturing level of some 80 million CSPs, with no more than 10 million being sourced by the subcontract industry.
By the year 2001, however, the subcontract volume will have increased to 0.4-0.6 billion at between 0.9- 1.5 cents per 1/O, depending on the package design and material content.
Figures 2. BPA's CSP and NCSP forecast
Figure 3. This figure compares the typical cost profile of an emerging technology to an existing one. Wafer Bumping
The total requirement for wafer bumping (both captive and merchant) includes die intended for mounting in conventional packages. In 1996, BPA estimates that there were some 9 million 125-,150- and 200 mm wafers bumped, with the value of the merchant sector (mainly in Japan) worth some $200 million.By 2001, the total wafer volume will increase to some 40 million, mainly 150- and 200 mm, with the merchant sector increasing by value to about $700-800 million.
The above does not include the opportunity for stud bumping where companies are already exploiting their investments in dedicated Au wire bonders to provide subcontract services both for whole wafers and individual die bumping.
High Density PC Boards
High density interconnects are needed to join increasing numbers of area array pads on CSPs, flip chips and for very fine pitch PQFPs.This requirement is leading to the development of new types of microvia PC boards by plasma etching, laser drilling or photo-imaging approaches.
Japanese Efforts
In Japan, efforts to develop these techniques have been rapidly increasing following IBM Yasu's photo-imaging build-up board for the "Think Pad" portable computer. The new substrates allow a reduced layer count, reduced weight and potentially lower cost.Ibiden, NEC and Sony have established photo-imaging technology, with Airex, Hitachi AIC and JVC now using laser drilling. Japanese output of these new high density boards is currently valued at around $700 million, with Europe and the USA estimated to produce about 20 percent of the total.
At the end of 1996, total production in Japan was 30-35,000 m2 per month with the expectation that by the end of 1997 requirements would triple. Since there are few companies in the west with microvia capabilities, the majority of requirements will initially be satisfied by Japanese sources.
The majority of build-up board production is captive (IBM, JVC, NEC, Sony, etc). IBM with its photo-via technology and JVC with laser-vias are currently the two largest makers, each producing some 5,000 m2 per month.
Ibiden is about to start mass production to supply the merchant market, and by the end of 1997, there will likely be some 15 companies in Japan qualified to offer microvia build-up boards. This growth is reflected in equipment demand.
For instance, at the end of 1996, there were some 30 laser drilling machines in use by Japanese companies to produce PC board microvias (80% supplied by Sumitomo Heavy Industries). It is forecast that by the end of 1997, there will be more than 80 laser drilling machines used in Japan.
Traditionally-built PC board output is valued worldwide at $30 billion. By early 1998, new boards will be worth some 7-8% of this value, which reflects an unprecedented rate of growth.
Contact Mr. Campbell, BPA's American Business Development Director, at 44.1306.875.500, fax 44.1306.888.179 or by e-mail at m.campbell@bta-ltd.co.ukfor more details and price of the study.