Dr. Sassan Raissi on Test

An expert looks at the issues

Dr. Sassan Raissi

Q: What are the key issues in testing CSPs?

A:Before we start, let me tell you that I am from the school of thought that CSP test is best done at the wafer level for at least 85% of devices. I will, however, give you my opinion of the issues at each level. In package form, the principal challenge for CSPs is in auto handling and contact. The accuracy of device placement has become increasingly critical over time and higher pincounts require increased contactor pressure.

CSPs don't actually introduce as many new problems to handling as they tend to aggravate existing problems. Smaller packages with finer lead pitches and more pins have challenged an industry that is simultaneously burdened with a requirement to lower the overall cost of test.

Q: What are the concerns in testing at the wafer level?

A: At the wafer level, contact is much easier than at the package level, but some users may be concerned about the integrity of the test,in theory, for RF, complex mixed signal and high performance digital devices. Due to the added inductance of the probe interface, RF devices tend to oscillate. High performance digital as well as analog signals are also negatively impacted by this inductance. 

Q: Is currently-available equipment adequate for testing?

A: The equipment now on the market is barely adequate for low pincount devices and is not sufficient for testing high pincount ICs. It is only a matter of time, however, until the equipment meets CSP requirements. The challenge in final test is to for equipment makers to develop handlers that can get the job done at a price that is commensurate with keeping costs down.

Q: What are the specific demands for testing CSPs?

A: We certainly have enough know-how and technology to address chip-scale packaging's demands, which are higher precision positioning equipment (stepper motors, tighter tolerances, etc.) and materials that will make good electrical contacting possible without using excessive force ( i.e., diamond particle interconnect, a process that incorporates nickle-plated diamond particles that result in excellent electrical contacting without scrubbing). Because the particles are sharp, they pierce the oxide on the contacts. These methods, however, are expensive.

Q: How soon will the necessary equipment be available?

A: As soon as ATE manufacturers sense the market demand, they will invest in the resources to produce the necessary equipment. It is essential that technology nearly always lead the marketplace, and market demand will invariably determine the status of the test infrastructure. The "technology stockpiling" of technological solutions that are not yet available to the production marketplace will change to implemented solutions when the market speaks with its wallet. That hasn't happened yet!

Q: What are the issues for wafer-level test?

A:While testing at the wafer level will present some new problems, the solution will, in the long run, be the solution to testing of all CSPs.

Eventually, I believe, CSP handling will be performed by a new class of equipment that is the combination of a prober and a device handler.

This will be a machine that is capable of physically handling the devices, or groups of devices, in various formats. This machine will present the devices to a sub-assembly that will contact the leads using prober technology, and will then perform additional functions through other processes, such as marking, scanning, singulation, etc. The end result will be ready-to-ship output in tape and reel or a similar format.

The integration of multiple functions in a single mainframe will lower capital acquisition costs of test equipment, offsetting the expense associates with the higher level of technology needed for CSPs.

Q: Along those lines, how will prober technology affect CSP test?

A:About 85% of the 50 billion devices that were tested last year are capable of being interfaced to the tester through existing probe technology. About 15% of the ICs that are tested, however, possess requirements beyond today's probing capabilities. At the rate probe technology is developing, it should be capable of handling all but the most difficult devices in the near future.

The solution will eliminate the need for two passes at device test (probe and final test), which will lower the cost of test per device.

What can users do to expedite CSP testability?

A: CSP designers should be working directly with handler manufacturers. The handler companies will benefit from early knowledge of the new packages. If there are options in how the packages may be processed, the handler engineers will be able to help steer those decisions in a way that will facilitate effective solutions suggesting a standardized location on the frames for alignment holes, for example.

What is the role of burn-in for CSPs?

A: Burn-in isn't about to go away, although many users wish that would happen due to the added cost and turnaround time. A socket capable of acceptable electrical contact that will survive the burn-in process is going to be a significant challenge. Burn-in board automated loaders and unloaders will have the same handling problems as the ATE device handlers.

In addition, burn-in sockets can damage CSP devices due to excessive clamping pressure when existing style sockets are used. The alternative is a hand-loaded socket that is clamped to an exact pressure. This method does not destroy the device but is very labor intensive and therefore very expensive.

Editor's Note: We interviewed Dr. Sassan Raissi for this special test issue. Dr. Raissi is president of Digital Testing Services Inc., Santa Clara, Calif., part of ISE Labs. ISE is one of the largest independent IC testing companies in the world with testing services offered through its Hong Kong, Singapore, San Jose and Santa Clara subsidiaries. Semiconductor packaging services are offered in its Manteca, Calif. Facility (formerly owned by the Alphatec Group.) Prior to co-founding Digital Testing Services in 1994, Dr. Raissi served in various posts at Fairchild Research Laboratories, San Jose, Calif., including that of operations manager for the Microprocessor Group. He holds a doctorate in applied mathematics from Washington State University, Pullman. Contact Dr. Raissi at 408.727.9206, fax 408.727.3136 or e-mail:sassan@dts.com