The evolution of a new wafer-level chip-size package

Research has led to the development of the wsCSP™, a wafer-level chip-size package that requries no thinfilm processing steps and requires less than 1mm mounted height on a PC board.

By Vincent DiCaprio, Markus Liebhard and Lee Smith, Amkor Technology, Inc., Scottsdale, Ariz. On a traditional IC assembly line, one chip is packaged at a time. By contrast, state-of-the-art device fabrication is a highly efficient operation with up to several hundred devices fabricated on each wafer at one time.

The evolution of batch processing from the wafer fab to the assembly line can increase production efficiency and lower the cost of IC packaging. In the continuing, industry-wide demand for smaller, lighter and less costly IC packages, wafer batch processes are becoming the new focus of chip packaging.

An entirely new group of chip-scale and chip-size packages (CSPs) is being developed to take advantage of the potential cost savings from batch processing on the backend. These CSPs are assembled directly on the silicon wafer and named wafer-level or wafer-scale CSPs.

Extending the Fabrication Process

Figure 1. Cross-sectional view of a wsCSP package.

One method of wafer-level packaging is an extension of the IC fabrication process where the wafers remain in the frontend environment during most of the assembly. A series of thinfilm manufacturing steps is being used to build the interface between the very fine geometry of the IC and the coarser geometry of the matching PC board. Eutectic solder balls are re§owed on the package to ensure compatibility with other standard surface mount components. Fujitsu's SuperCSP™1 and FlipChip Technology's UltraCSP™2 both employ a similar approach to wafer-level packaging. Amkor Technology Inc. and Anam Semiconductor Inc. have teamed-up to develop a wafer-scale CSP (wsCSP) that requires no thinfilm processing steps (Figure 1). A fairly typical IC assembly flow is maintained, and efficiency is increased through wafer-level processing.



The resulting product is a true chip-size package, i.e. the package is exactly the same size as the actual chip in x and y directions and requires less than 1 mm mounted height on the board. By using §exible polyimide circuit tape for the redistribution layer, excellent board level reliability is achieved with standard JEDEC solder ball sizes and pitches.

Market Outlook

A wide range of market forecasts for the adoption of emerging wafer-level packaging technologies exists. TechSearch International, Austin, Texas, recently devoted a section of its "Fourth Quarter 1998 BGA Development Update Service" to wafer-level packaging.

Figure 2. Wafer-Level IC package market forecast.

According to E. Jan Vardaman, president of TechSearch International, "It is difficult to group wafer-evel packages into categories, but it is a necessary step in understanding the technology. Many of the options listed as wafer-level packaging are identical to flip-chip technology using a redistribution layer. "One might argue that §ip-chip technology is really just packaging at the wafer level, but many companies want their approach to be considered a CSP. Amkor and Anam have developed a novel approach that leverages their existing CSP supply base and packaging technology to deliver wafer level CSP cost and performance benefits."

(Figure 2 shows TechSearch's January 1999 market forecast for adoption of wafer level IC packages, while Figure 3 illustrates the process flow.)

A Low-Cost Solution

In addition to the highly efficient batch processes utilized in wsCSP packaging, several other factors contribute to the excellent, low cost potential of this assembly process. These factors include:

Figure 3. wsCSP assembly flow chart illustrates the process from receipt of the customer's wafer through the shipping of singulated devices.

Materials Availability From the flexible substrate tape to the epoxy encapsulant to the lead-tin solder balls, all materials used for wsCSP assembly are readily available and commonly used in IC packaging. No cost premium for special materials contributes to the wsCSP pricing. At high volume assembly, the lowest possible material cost can be realized. The circuit tape manufacturing is state of the art PC board or wide-web continuous tape technology. Depending on the design requirements, in terms of line and space widths, the substrate tape can be manufactured in PC board panel format or on a wide-web reel-to-reel line. The absence of windows or holes in the polyimide tape during manufacturing, and because no freely suspended traces or leads are necessary, excellent tape yields in both panel and continuous processing are possible.

Capital Equipment The switch from individual chip to wafer-level processing required the development of only one specialized piece of equipment, the wafer laminator. All other processes take advantage of existing equipment technology, or only minor modifications were necessary.

Even though the wafer laminator is newly developed equipment, the results show that cost savings can be realized by introducing the laminator into the assembly §ow. The equipment allows batch process lamination, one wafer at a time.

Several individual die attach stations would otherwise be needed to achieve equal unit throughput in a CSP die attach strip line.

For the circuit tape preparation, conventional roll lamination and tape punching is possible. Both are established processes, albeit from other industries, and they operate in a highly efficient and continuous manner.

Minor Modifications

The minor modifications that were necessary for the wire bonder, stencil printer, and ball attach equipment included the addition of automated wafer handling capability and a vacuum wafer chuck as the work platform. The wafer mounter, dicing and pick-and-place equipment needed no modifications.

Reject Management Since all wafers are typically probed for functionality before assembly, the information from the prober is used to increase the efficiency of the bottleneck assembly operation, wire bonding. Software capability to read and act upon an internally standardized wafer map was implemented on the large area wire bonder.

Incoming wafers that are ink marked only at wafer probing will be scanned and a wafer map will be created. Wafers that are supplied for assembly with a wafer map need not be scanned. These wafer maps will be translated to the internal standard format. A barcode ID label is used to identify and trace the wafers.

Upon loading the wafer onto the wire bonder's work platform, the wafer ID label is read and the "according" wafer map is accessed. The reject information of the wafer map allows the wire bonder to skip bad devices and bond only the functional ones.

The same or possibly an updated wafer map is used at the pick-and-place station to select only good units for marking, packing and shipping.

Test Advantages

Since the entire wsCSP assembly is done in wafer form, final electrical test and burn-in can also be efficiently accomplished in non-singulated form. While final electrical test can be performed in wafer form today, wafer level burn-in for wsCSPmay still be a few months in the future.

Figure 4. Front and back of wsCSP samples; one edge row design and two center row designs are shown.

An existing wafer probe station can be used to handle the wsCSP wafer and access the individual devices on the wafer. The commonly used titanium Pogo pins for wafer probing are replaced by an array of pins that allow contacting solder balls, which results in minimal ball deformation. This array of contacts is automatically stepped across the wafer to test all devices. Cost savings during final testing and burn-in at wafer level can be realized through both the elimination of expensive sockets and the reduction of handling issues for very small devices. Due to the relatively large ball pitch of a wsCSP device, compared to its bond pad pitch, probe cards for final testing can carry multiple pin arrays allowing the parallel testing of several devices on one wafer. Efficient parallel burn-in can be achieved with the appropriate wafer level burn-in contactor.

For high-yielding wafers during IC manufacturing, the elimination of wafer probing before assembly is conceivable. Cost savings from eliminating an entire test process step, is believed to outweigh the additional cost of wire bonding a few reject units. Final testing will still assure that only good units reach the customer.

Customers that prefer to perform final test inhouse, can take advantage of the same test strategy on wsCSP, and the assembled wafers can be shipped in an unsingulated form.

Proven Process

Figure 5. The 200mm wsCSP format and pre-singulation close up.

The described assembly flow was successfully proven in the Amkor/Anam wsCSP pilot line, on both 150 mm and 200 mm wafers. Several different customer devices on 150 mm wafers were assembled and returned for reliability testing and analysis in parallel with Amkor reliability testing. Both center row designs (with the die bond pads concentrated in one line across the die center), and edge row designs (with the die bond pads along two or more die edges), were successfully assembled and singulated. Examples are shown in Figure 4.

To prove 200 mm capability, a 9.0 mm by 11.0 mm daisy chain device was designed and manufactured in the Amkor/Anam wafer fab. This device has 54 I/O in a 9x(8-2) center row array, with a ball pitch of 0.8 mm in one direction and 1.0 mm in the other direction. It was designed to simulate the size and I/O configuration of a DRAM device.

All assembly processes were adjusted for and verified on these 200 mm wafers (Figure 5). The final packages were submitted for internal qual "C" testing.

Like most other true CSPs, the wsCSP offers significant benefits to the system manufacturer. Some of these benefits are shown in Table 1.

Limitations and Applications

To be packaged as a true CSP, a semiconductor device must meet the minimum die size required to accommodate all electrical connections in a ball array of the desired pitch on the available die surface area.

Since the minimum feasible SMT ball pitch today is 0.5 mm, the die size of CSPs must be relatively large. This requirement is also referred to as the "fan-in" requirement, indicating that all traces from the die bond pads to the ball land pads must remain within the die area. This requirement is the single most limiting factor for wsCSP packaging, and it restricts this assembly technology to relatively low density devices.

Today, most SRAM, DRAM and Flash memory devices can theoretically be accommodated in the wsCSP format. However, die bond pad layout is most often another reason for incompatibility with wsCSP assembly.

The die designer has to follow certain layout guidelines to accommodate easy device assembly with the wsCSP. The die bond pads should be lined up in a center row or two- or four-edge rows. The first and last bond pad of each row should maintain a minimum distance from the die edge. If these requirements are met, the device is a candidate for assembly in the wsCSP.

Due to the continuing improvement of fab technology and the aggressive shrinking of silicon features, the memory devices that can be assembled as wsCSP today may no longer accommodate the necessary ball array after two or three die shrinks, in which case, packaging as a true CSP or even near-CSP may not be possible.

A continuation of the wsCSP development is already under way at Amkor/Anam with a code-named advanced CSP, which will be identical in structure to the wsCSP. The new format, however, will allow the necessary fan-out designs, and will be comparable to the wsCSP in its low cost packaging approach.

Table 2. Electrical Simulation Results Summary

This article describes a new wafer level packaging process that does not rely on fab thinfilm processes. This process is currently undergoing final development and qualification (Amkor's Qual "C" level) in cooperation between Amkor Technology Inc. and Anam Semiconductor Inc.

The two companies hold several patents for both package structure and processes to manufacture this CSP. A manufacturing license agreement, combined with technology transfer options, is available from Amkor Technology Inc. The low-cost potential of the wsCSP package is due to several factors, including, batch processing, available common materials, equipment and the potentially large savings for electrical test.

There are opportunities for co-development of refined test strategies with Amkor Technology Inc.

Silicon devices of relatively low I/O density, i.e. SRAM, DRAM, FLASH, and Logic are best suited for wsCSP assembly. The die-down configuration provides for very good electrical properties. Because of the assembly on the silicon wafer, only fan-in designs are possible with the wsCSP. Wafers up to 8" diameter can be processed today, and high-volume production will start in the third quarter.

References

1. M. Hou, "Wafer Level Packaging For CSPs," Semiconductor International, July 1998, p.305.
2. P. Elenius and H. Yang, "The Ultra CSP Wafer-Scale Package," HDI, October 1998, p. 36.

Mr. DiCaprio is the director of chip scale products at Amkor Technology. He was previously product manager for advanced BGA packages at Amkor. Prior to joining the company in 1996, Mr. DiCaprio worked for IBM on the development and deployment of known-good die for flip-chip packages and the development and use of tape BGAs. He received a bachelor's in engineering from Concordia University, Montreal, Canada. Contact him at vdica@amkor.com.

Mr. Liebhard is product manager of wsCSP in the Advanced Product Development Group at Amkor Technology Inc. His experience in the semiconductor industry includes a position as sustaining engineer for Olin's µBGA™ in Manteca, Calif., and as equipment development engineer for the µBGA package at Amkor. Mr. Liebhard received a master's degree in materials engineering from the Swiss Federal Institute of Technology in Zurich, Switzerland. Contact him at mlieb@amkor.com.

Mr. Smith is the product marketing manager at Amkor Technology, Inc., responsible for strategic marketing. Prior to joining Amkor, he had 17 years of product engineering and marketing responsibility in the flexible circuits industry with Sheldahl Inc., ADFlex Solutions and Rogers Corporation. He received a bachelor's degree in industrial technology from the University of Wisconsin. Contact him at lsmit@amkor.com.