May - June 1999
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Comparing Chip-Scale Packaging to Direct Chip Attach
While direct chip attach offers the ultimate package solution-since there's no package at all-the chip-scale package is the clear winner today.
By Dr. Rao Mahidhara, Technical Editor
The evolution of the integrated circuit and the semiconductor industry's drive for performance, function and price are the key factors that have culminated in a double-digit, year-to-year growth for semiconductors over the last decade. That growth is projected to reach a total of 75 billion semiconductors/year by the end of 20011.
The continuing goal has been to optimize the performance of the silicon by minimizing signal losses attributed to the chip interconnect and the package—a challenge not to be taken lightly.
Industry drivers continue to be the demands for performance, miniaturization and price. Technology breakthroughs enable continued miniaturization as well as electrical and thermal enhancement. Denser circuitry and significantly higher I/O interconnections approaching 1000, are the result of a focus on performance to support higher clock speeds (>250 MHz).
Wirebonding Technology
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| Figure 1. National Technology Roadmap shows increasing I/O densities and clock speeds. (Source: Semiconductor Industry Association) |
"Industry drivers continue to be the demands for performance, miniaturization and price."For the past decade, industry observers have claimed that the physical limitations of wirebonding will soon diminish its utility as an assembly method. However, the demarcation line where wirebonding can/cannot be used is a moving target. Ultimately, however, in a decade or two, wirebonding will largely be replaced by other, newer technologies.
Advanced Processes
Leading edge IC manufacturers are expected to offer semiconductors based on advanced lithography processes, with feature sizes approaching 0.18 micron and 0.10 micron, by next year and 2006, respectively2.Over the years, more and more functions have been packed into denser chips but this system integration presents few problems. With the reduction of feature sizes and the continued functional integration of ICs, there is growing need to manage a much greater number of I/O off-chip.
Product Miniaturization
Semiconductor packaging has undergone significant miniaturization in the past two years, driven by the design requirements of the portable computing and mobile communications equipment markets.New innovations, such as direct chip attach (DCA) where the flip-chip IC is directly attached to the board, and chip-scale packaging, have been moving swiftly to meet the growing needs of miniaturization, performance and function-driven customers. Arguably, DCA and chip-scale packaging (figure 1) constitute today's hottest packaging solutions. As the experts point out, the need for product miniaturization has caused the rapid adoption of these technologies3.
The Roots
Growing interest in the high conduction speed and small size of flip chip makes it easy to forget that DCA is not really new.In the 1960s, solder bumps were used as interconnects with IBM's Controlled Collapse Chip Connection (C4) process4. Later, underfill was added to protect solder bumps from environmental factors.
In contrast to the classic C4 process, state-of-the-art flip-chip assembly uses organic substrates for DCA or flip-chip on board (FCOB) technology. The latter was originally introduced by Motorola to achieve the smallest component size possible by completely eliminating all the features associated with conventional packaging for integrated circuits.
"In contrast to the classic C4 process, state-of-the-art flip-chip assembly uses organic substrates for DCA or flip-chip on board (FCOB) technology."The principal "bare die" or DCA methods now employed are wirebonding (conventional COB) and flip-chip bonding (figure 2). These methods have been in use for certain applications for many years, and the flip-chip process is now poised for a major extension in use industry-wide. Compared to a conventional or even chip-scale package, DCA offers a lower PC board height, weight and footprint.
Chip-scale packages, on the other hand, have entered the mainstream of the microelectronics market. In 1997, CSPs gained momentum by their adoption in the FLASH memory market, and last year, the CSP broke through as a volume semiconductor packaging technology for consumer products.
Several hundred different CSP formats are currently under development, and differ depending on I/O density/interposer/die design combinations. CSPs are generally separated into four types:
- Flex/circuit/tape
- Rigid substrate
- Custom leadframe
- Wafer-level CSPs5
Drivers
Additional drivers for the DCA include, the evolution of wafers with copper pads for increased speed, low dielectric Dk inner layers, high frequency ICs and decreasing die sizes and features features which result in reduced bond pitch7.
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CSP/DCA Drivers
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With the recent emergence of wafer-level chip-scale packaging, the relentless drive for low cost and high yield through batch processing at the wafer level is a key consideration at several companies.
Wafer-level packaging is a niche market today. Among the enablers for wafer-level packaging are, the availability of wafers with copper pads, wafer-level test and burn-in, integrating passive devices, design tools and wafer bumping.
"Several barriers to DCA exist including die cost, thermal management, design tools, redistribution and standards."Global consumption of flip-chip devices will increase from 1.5 billion this year to 3 billion in 2001, according to Electronic Trend Publication, San Jose, Calif. By 2001, the main uses of DCA will be in rigid disk drives (23.3%), displays (10.1%), computers (11.4%), cell phones/pagers (11.4%), telecommunications (7.7%), automotive (13.1%), watches (6.9%), consumer and medical applications (6.0%).
Overall, the rigid/flex CSP and DCA will carve out a significant market3 among the different interconnect technologies. CSP growth is predicted to exceed 250 million units this year, climbing to more than two billion units in 2002, according to ETP.
Road Blocks
Several barriers to DCA exist, as noted, including higher die cost, thermal management issues, expensive die design tools, the limitation of redistribution technologies and standards7.Compared to standard surface mount assembly, the assembly processes for CSPs and DCAs are both costly and time consuming. In addition, they are not yet capable of low cost, high volume production because of numerous processing steps, large floor-space requirements and the limitations of some materials.
HDI Substrates
Miniaturization results in smaller pitch package and, higher interconnect density, so that PC board pitch has to decrease to be compatible with the package. Conventional board constructions cannot handle grid arrays with high I/O and/or pitches below 0.5 mm.10
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| Figure 2. Product miniaturization is a rapidly evolving trend which is strongly affecting IC packages. |
These factors will result in expensive substrates for DCA and CSP applications and add to the overall cost of DCA and CSP technologies at high I/O and/or pitches <0.5 mm. According to industry experts, substrate cost is generally 30% of the overall package cost. In addition to higher I/Os, greater heat dissipation in the next generation PWBs will be an important challenge that must be met3.
The Challenges
Both DCA and chip-scale packaging offer both positive attributes and limitations. It is useful, therefore, to assess how CSPs will be accepted in light of a growing DCA market by considering several key issues:(a) Higher die and packaging cost—Drivers on the die side are copper pads and low Dk dielectrics. The introduction of high speed wafers with copper pads by IBM, and low Dk dielectrics, require unique combinations of metallurgies and metal deposition techniques. These combinations must be compatible with a high modulus dielectric layer under the pads.
(b) Aluminum vs. copper pads—Wirebonding over aluminum pads is well established. It is a low-cost and mature technology. The introduction of copper pads places stringent demands on metalization schemes over copper for wirebonding, and promotes higher die and package costs for DCA and CSP applications.
In addition, placing solder bumps on wirebond pads of the die for flip-chip-DCA is not practical in most cases because the fine pad pitches result in bump sizes too small for reliable solder joints. This situation can be overcome by redesigning the device or providing a "rerouting" layer on the die surface leading to higher die cost.
Several companies and electronic manufacturing services (EMS) are now actively pursuing low-cost W/B-DCA, involving bonding to copper pads and the use of low Dk dielectrics to package 40-60 I/Os fast SRAMs7.
The CSP size and array, on the other hand, remain constant, which is an advantage, irrespective of die shrink and become transparent to the user. The CSP will then be larger than an equivalent foot-print on the module, but not by more than 20-30% (This compares to the more conventional packages which are 3-10x the size of the die they contain).
(c) Thermal issues—The absence of an interposer between the die and the PC board leads to efficient thermal management from the small die surface in the FC-DCA. On the other hand, several companies developing low I/O CSPs report a dramatic enhancement in thermal properties over TSOPs, because of small package size and weight, which incidentally are close to that of FC-DCA.
Large die (>1.2mm), however, operating at moderate to high performance, pose significant thermal challenges for CSPs or DCA and thermal transients become important and warrant the use of heat sinks for low power application.
(d) Board substrates—The HDI substrate issue for FC-DCA using high I/O dies will be a major concern. These substrates will have to be designed to accommodate high I/O density using new and more expensive HDI board technologies.
Low-cost conventional board technologies will not be able to serve the high trace density needs of die with high I/O density.
These substrates will have to be made with novel materials and processes that can efficiently manage the heat dissipated by these high I/O die. All these factors, in turn, add to the overall cost of the substrates.
Fortunately, conventional board technologies can meet the growing needs of low I/O CSP markets, and, therefore, constitute an important advantage for CSPs over FC-DCA. The organic substrates used in the construction of CSPs provide a better answer to the thermal expansion characteristics of the module substrates.
(e) Underfill—DCA requires underfill to reduce the stress on the solder balls due to TCE mismatch between the silicon and substrate13. In contrast, CSPs have been designed primarily to eliminate the need for underfill during second level assembly. Consequently, CSP rework has never been an issue.
Needless to say, it is easier to control underfill for low I/O flip chip at the package level than it is on the main board with current assembly process. This situation imposes difficulties during rework.
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| Figure 3. Amkor Technology's micro lead frame package is representative of today's CSPs |
(h) Redistribution technologies-The need for a flip-chip option started redistribution technologies. In this context, Amkor, particularly, has found that W/B DCA is more reliable and cost-effective than FC-DCA. Redistribution technologies may contribute to added cost and reliability concerns. However, National Semiconductor's reliable and low-cost Op-Amp package adopts flip-chip technology at the wafer level with no redistribution.
(i) Handling-The presence of bumps under the die surface adds some environmental protection to the die pads, but the active surface of the die is still virtually exposed and subject to mechanical damage. Testing after bonding, followed by encapsulation, is difficult and leads to higher cost7. The interposer in CSPs helps ease its testing and handling3.
(j) Testing-DCA rework is a key issue3. Furthermore, probe pins lead to design and real estate issues and enhance the cost and difficulty of testing FC-DCA even farther. In addition, board deformation during testing is another problem14.
CSPs, on the other hand, can be more easily tested these days because of the existence of a rapidly maturing infrastructure.
(k) Assembly-Assembly infrastructure exists using current assembly processes for the production of low I/O FC-DCA, where underfilling is necessary to relieve stress on the solder joints for high frequency wireless applications. Infrastructure for high I/O count FC-DCA is still in its infancy. Anisotropic conductive paste is used for FC-DCA in Japan to attach low thermal resistance and highly reliable gold bumps to board is not SMT compatible13.
On the other hand, the absence of underfill to assemble CSPs becomes conceptually simple. In addition, the CSP assembly infrastructure is SMT compatible and maturing to a level of high volume production capability. For both approaches, however, some modification of conventional processes is probably required to adapt to the fine pitches and small size of the components.
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| Figure 4. The increasing popularity of flip-chip technology is responsible for the new assembly equipment, such as this Model 9002 FC/CSP die attach machine which dispenses, bonds and cures in one system. |
(n) Standards-No official standards or guidelines are available for the FC-DCA outlines and the assembly process is die dependent. Interconnection pitch is strongly dependent on die pad pitch and can be changed using a redistribution layer on the die surface. Standards and guidelines for CSPs have rapidly evolved through JEDEC and EIAJ.
Conclusion
When the die is designed as an array, and substrate technologies are available, solder bumping technology for DCA is an attractive solution for cost and performance."ƒthe relentless drive for low cost and high yield through batch processing at the wafer level is a key consideration of many companies."The use of underfill to reduce the stress on the interconnects is a necessity with DCA and a serious road block to ease of rework. Underfill increases the cost of assembly, particularly at low I/O densities, but can be cost-effective at higher I/O densities (>500).
For all other die designs, the use of CSPs appears to be a better and more rugged alternative than FC-DCA. CSPs can be applied to any wirebonded device and provide most of the size advantage of flip chip.
The CSP assembly infrastructure is quickly maturing to a high-volume level to meet the growing demands of portable equipment markets. CSPs, with their coarser array pitches, place a smaller burden on substrate manufacturing capability and module assembly processes.
Suppliers treat CSPs like any other package, thus quality assurance through handling and testing becomes an important issue to satisfy the end-users. From a semiconductor supplier's standpoint, CSPs are the most promising choice.
References
- Electronic Trend Publications, IC Packaging Trends, 1997, San Jose.
- Semiconductor Industry Association, National Technology Roadmap for Semiconductors, 1997, San Jose.
- M. Chason, Symposium on DCA and CSP, NEPCON West, Anaheim, Calif., Nov. 22, 1999, p.1.
- J. Lau (Editor), Flip Chip Technologies, McGraw-Hill, New York, 1996.
- S. Greathouse, Proc. Surface Mount International, San Jose, Calif., 1996.
- T. Zhou, Symposium on DCA and CSP, NEPCON West, 1999.
- L. Smith, NEPCON West, Nov. 23, 1999.
- T. Di Stefano, Symposium on DCA and CSP, NEPCON West, Nov. 22, 1999.
- W. Sui, Ibid.
- K. V. Guinn and R. Frye, "Flip Chip and CSP I/O Density Requirements and PWB Capabilities," Proc.of ECTC, p. 649, 1997.
- R. Mahidhara, "Substrate Requirements for Chip-Scale Packaging," Chip Scale Review, January/February 1999, p. 5.
- P. Thompson, Symposium on DCA and CSP, NEPCON West, Nov. 22, 1999.
- J. Lau, Ibid.
- H. -J. Albrecht, Ibid.