The Impact of Chip-Scale Packaging on Bare Board Electrical Test

By Joseph Fjelstad, Tessera Inc., San Jose, Calif.

chip-scale packaging offers significant opportunities to the developers of electronic products. the technology, however, also carries with it many challenges to those elements of the electronics manufacturing infrastructure needed for support, such as electrical test

The advent of the chip-scale package has been among the most widely heralded events in the recent history of electronics. The reasons for this attention are numerous, but two central points are key: First, chip-scale packages are small, very nearly as small as the chip itself in terms of total volume, and exactly the same size in area in the case of chip-size packages.

"In Japan... the advantages of chip-scale packaging were immediately comprehended."

Figure 1. Chip-scale packaging technology combines the important benefits of flip-chip technology with the many advantages of surface mount technology.

In Japan, the world leaders in compact electronics, the advantages of chip-scale packaging were immediately comprehended. The results of that early understanding are visible all around us in the form of smaller and lighter portable electronics. The journey was not bump-free, however. Standard substrate technology was pressed to its limits and new substrate technologies had to be developed. This follows the long history of the oft-strained relationship between packaging and substrate, with packaging driving substrate technology.

Finer Lines and Spaces

Making finer lines and spaces, while important, offered only limited benefits. Smaller holes were required to win the necessary real estate to accomplish the routing; however, the large aspect ratio of board thickness to hole diameter made reliable plating of the throughhole difficult. Fortunately, newer schemes were developed that took inspiration from much of the work that had been done on multichip modules. In fact, almost all of the processes being developed or offered can trace their technical roots to MCMs. The major departure is in the materials and some of the processing tools used.

"The introduction of the plastic BGA packageƒ was the door-opener for chip-scale packaging."

Process advances in substrate manufacturing technology has taken two separate paths: sequential processing and parallel processing, with a number of variations of each.

Figure 2. Examples of µBGA® chip scale packages for flash memory and RDRAM® (far right) are shown.

Sequential processing is the most commonly reported on and the type produced in the largest volume. The process involves building up the board layer-by-layer on a core, which is often a multilayer PC board. In contrast, parallel processing is accomplished most often by co-laminating full or partially preprocessed circuit layers. Interconnection between layers is achieved during the lamination process. Both general methods are supported by a number of different process tools such as lasers, plasma and photo-imageable polymers. (A matrix of the different process options is shown in Figure 3.) The advances achieved in circuit substrate manufacturing technology placed immediate pressure on the manufacturing support areas of inspection and test.

The Road to CSPs

The introduction of the plastic BGA package in the early 1990s was the door-opener for chip-scale packaging. BGAs were warmly received by the electronics industry as a general solution to a packaging problem that was becoming more serious with each new generation of integrated circuits.

Moore's Law, the predictor of a relentless doubling of transistor density every 18 to 24 months, was placing increasing demand on packaging and interconnection technologies. It had become very clear that peripherally leaded packages had reached their practical limit, in terms of performance.

Coming from another direction, but also pushing for change, were the assemblers who found yields on their boards dropping to unacceptable levels due to the delicate, fine-pitch metal leads on peripherally leaded packages. Area array packages, however, provided the necessary answer—one that would allow the electronics industry to continue its "march toward the asymptote" in terms of reducing the cost of electronics while meeting incessant industry demands for smaller and faster electronics.

While IBM and others had been using array interconnection concepts for some years, and the use of pin grid arrays was well established, the introduction of ball grid array technology (BGA) marked the electronics industry's broad entry into the "Age of Area Array."

Smaller Packages

Once concerns over the fact that most of the solder joints were hidden by the package were assuaged, the stage was set for package size reductions and the introduction of the chip-scale package. It took some time (and no small amount of research) but the industry was finally able to convince itself that it was possible to make smaller packages.

As confidence in the technology rose, lead pitches on area array packages were reduced from 1.27 mm to 1.0 mm then down to 0.8 mm, 0.75 mm, 0.65 mm and 0.5 mm—the realm of the CSP. All were soon being offered as package choices and all could be easily assembled at high yield, but it was becoming clearer that testing was going to limit the technology.

The Dilemma

One of the first issues that impact test is component lead pitch. Lead pitch is one of the primary pacing elements of test. Consider that the proliferation of different grid pitches for area array packages appears to have proceeded with little concern or appreciation for the intrinsic power of grid-based interconnection to vastly improve the future design/manufacturer/test paradigm.

In the past, peripherally leaded devices employed what has been called, "The 80% Rule," which has been used to determine lead pitch shrinks, purportedly based on the combined manufacturing capabilities of the printed circuit board manufacturer and the printed circuit board assembler. Thus, in practice, a 1.0 mm pitch would be followed by a 0.8 mm pitch, which would be followed by 0.65 mm pitch and so on. The rule worked well enough for peripherally leaded devices, but it was a fairly arbitrary convention. As indicated earlier, IC packaging companies around the world seem to be blindly using that same 80% rule concept for area arrays, as well. Unfortunately, that rule doesn't take full advantage of the intrinsic opportunity offered by area-array geometry.

"The 60% rule calls for ball diameters to be reduced by 60% with each I/O pitch reduction."

Figure 4. At left are overlapping grids for 9x9, fully populated arrays of 0.5 mm, 0.65 mm, 0.75 mm, 0.8 mm and 1.0 mm. These are shown with a single land size for clarity. (The solder land size commonly changes with the lead pitch). At right are overlapping grids for devices with a common base grid pitch of 0.5 mm. The moirÚ pattern on the left is an early indicator of the difficulties that lay ahead for component placement, routing, electrical test and socket manufacture.

In response to the limits of electromechanical probing, newer methods are being developed which promise to greatly facilitate electrical testing of high-density boards, such as those required to support chip-scale packaging. Electron beam and laser/plasma methods have both been described. Predicated on the detection of localized ejection of electrons caused by the stimulation of test nodes with the electron beam of laser, these non-contact methods are more sophisticated than the more prosaic electromechanical methods the PC board industry and its customers have become accustomed to. The equipment is also more expensive, and, as yet, is not totally proven in a manufacturing environment. Still, the fact that non-contact probing promises very high test rates for fine-pitch arrays, such as those that will be required by next generation packages, warrants a careful look at these technologies as they develop and mature.

A final enticement to the use of non-contact testing is the fact that the contact points are not disturbed. As lead pitches continue to shrink, concern over the integrity of the joining land increases. Electromechanical probes are capable of damaging or contaminating solder or bonding lands. On the other hand, non-contact probe systems, like electromechanical probing systems, appear capable of giving a good test report to lands which have a thin layer of latent soldermask. Such conditions will likely result in failure of the solder joint even though the board is good.

Complicating Factors

While the electrical test solutions for opens and shorts are becoming available, there is still a need to address a range of new challenges based on concepts that integrate passive electronic functions into the PC boards. Integrated passives, such as buried resistors, capacitors and inductors are being employed on an increasing basis. While these concepts promise to reduce the number of test points that must be contacted, they place a new burden on the test system to determine if the values associated with these "components" are correct.

The challenges of electrical test are really predicated on the fact that the technology must respond to the choices made by the semiconductor packager, who, at least in theory, is responding to the needs of the PC board manufacturing community.

The element often left out of the decision, or so it seems, has always been electrical test. It has simply been assumed that the solutions would be forthcoming. This mentality, in all probability, was carried over from the halcyon days of throughhole technology, when all elements of the electronics industry from IC packaging to PC board design, manufacture, assembly and test worked together in seamless harmony.

The cornerstone of this synergistic relationship was a common grid pitch. 100-mil center lead pitches for all components provided all participants with the ability to anticipate and respond with confidence to the needs of their discipline. However, the advent of surface mount technology pulled the cornerstone out and caused the structure to collapse.

Lead pitches were suddenly allowed to float based on the needs and capabilities of board design, manufacture and the assembly process. Electrical test was left to find its own way in a now-gridless world. Area-array packaging offers a chance to return to those halcyon days. However, the industry has yet to collectively grasp the intrinsic value offered by area array packaging concepts. It is also reluctant to change. Still, the advantages are compelling and the technology itself will make a cogent argument to anyone who will listen to its message.

Figure 5. A single, fundamental base grid pitch provides a cleared vision to work on the opportunities of the future while providing solutions for today that will still be useable for years into the future.

As described earlier, there are many lead pitches in area array packaging. It is important to understand that IC suppliers can provide components with virtually any lead pitch they choose—or more importantly—any lead pitch demanded by the customer. An opportunity now exists to have the system make sense without penalizing any particular element of the infrastructure. This can be accomplished by adopting and sticking to a fundamental base grid pitch. The impact could be phenomenal. Recommended Baseline

To demonstrate, look at figure 4. A fundamental base grid pitch of 0.5 mm is being recommended as the canonical baseline for area array packages. The reasoning is as follows:

1. It is the point where JEDEC and EIAJ roadmaps converge relative to IC packaging.
2. It is consistent with IEC Publication 97, Standard Grids for Printed Circuits, a document which has been adopted by ANSI and the IPC (ANSI/IPC-1902).
3. A common grid pitch will help ease component placement and board layout difficulties.

1. J. Fjelstad, "Exploiting the Opportunity of Area Array Packaging," Electronic Packaging & Production, February 1999.
2. T. Di Stefano and J. Fjelstad, "The Expanding Chip-Scale Electronics Infrastructure," MEPTEC Report, July/August 1998 .
3. C. Vaucher, "The Basics of Electrical Test and Its Stakes," The Board Authority, March 1999.

Mr. Fjelstad is recognized internationally as a CSP expert. He is the author of numerous publications, including Flexible Circuit Technology, second edition. He is a Tessera senior engineer and a Tessera Fellow. Readers may contact him at joef@tessera.com or by phone at 408.383.3611. This article is based on a paper presented at the 1999 IPC/CCA National Conference on Bare Board and Advanced Substrate Electrical Test, May 20-21, San Jose.