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Features Putting X-Rays to the Test Putting x-rays to use as an inspection tool can detect bad solder joints between board and package and a host of other problems. By Ron Iscoff, Editor The evolution of a new wafer-level chip-size package Research has led to the development of the wsCSP™, a wafer-level chip-size package that requries no thinfilm processing steps and requires less than 1mm mounted height on a PC board. By Vincent DiCaprio, Markus Liebhard and Lee Smith, Amkor Technology, Inc., Scottsdale, Ariz. Technical Forum Packaging Integrated Passive Devices at the Wafer-Level Wafer-level packaging is an enabling technology that will help drive widespread adoption of integrated passives and passive-intensive RF subsystems. The technology has an impact beyond providing lower packaging costs, higher product performance and smaller footprints. Wafer-level packaging also allows companies that have a wafer fab to bring packaging inhouse, using their installed equipment base. By James L. Young, Intarsia Corp., Fremont, Calif.