May - June 1999
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NEC's Wafer-Level Chip-Scale Package Offers Economics of Scale
By David Francis and Linda Jardine International Interconnection Intelligence, Montara, Calif.
Patent Number:
5,844,304
Assignee:
NEC Corporation
Inventors:K. Kata and S. Chikaki
Title:Process for Manufacturing Semiconductor Device and Semiconductor Wafer.
The increasing functionality of devices and the demand for smaller packages with increased performance at lower cost continue to drive packaging technology to greater use of chip-scale packaging.
Increased functionality is typically accompanied by increases in I/O counts, and with perimeter pad designs it becomes increasingly difficult to use wire bonding and/or TAB bonding for the interconnections.
Flip chip, which is desirable for high I/O applications, also offers excellent electrical performance. However, assembly limitations make the technology more suitable for higher-end applications.
While CSPs can be assembled at the chip-level like conventional packaging, the next evolutionary step is to apply the package while in the wafer stage. This approach yields the economies of scale needed for future product generations.
The patent described below is one of a small but growing number for wafer-level CSPs.
Wafer Process
The process begins with a standard wafer which has aluminum bond pads arranged around the periphery of each die. A passivation layer of polyimide, silicon nitride or silicon oxide is applied across the entire wafer using any standard deposition process.The passivation layer is patterned to open access to each bond pad as shown in Figure 1A. The thickness of the passivation layer is less than 20 mm.
A layer of aluminum (1 mm thick) is deposited on the wafer and patterned to provide the desired next level interconnect structure (Figure 1B).
While the word "redistribution" was not used, this metallization layer can be used to relocate the bond pads from a perimeter format to area array. The degree to which this is done depends on the number of I/O.
Figure 2A shows a 5-10 mm layer of nickel plated on top of the aluminum traces. The patent does not say whether it is electrolytic or electroless nickel. The later would seem to be the best choice because it is very good at sealing any porosity that exists in the aluminum film.
The nickel layer provides a number of functions in addition to sealing. The nickel is wettable by solder. It bonds well to aluminum and it acts to absorb the thermal stress that is generated when the device is mounted on a conventional PWB.
Other metals, such as copper, can be used provided they possess the necessary adhesion and diffusion barrier properties. Figure 2B shows the application of a top passivating layer of polyimide with a thickness of 20 mm or less.
This layer is patterned to expose a suitable pad area on each nickel-coated aluminum trace. It is desirable to plate a thin layer of gold on the exposed nickel pads to enhance solder wetting.
Bumping Process
The wafer is coated with a layer of flux, and solder preforms are applied to each of the bump sites. The preforms are made by punching with a die from a strip of solder. The flux holds the preforms in place until reflow. The wafer is then heated to reflow the solder and cleaned. The final step in the process is to saw the devices into individual chip-scale packages ready for assembly.International Interconnection Intelligence is a market and technology research company specializing in the semiconductor packaging and interconnection areas. Contact David Francis or Linda Jardine by e-mail at iii1@ix.netcom.com or by phone at 650.728.5270.
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| Figure 1A. A standard wafer with perimeter pads of aluminum is coated with a passivating layer and openings are created to access each pad. | Figure 1B. A layer of aluminum is deposited and patterned to form the next level interconnect and which may function as a redistribution layer from peripheral to area array pads. |