Wafer-Level Packaging: The Ultimate or Just Another CSP?

Robert Crowley
Contributing Editor

During the last year, wafer-level packaging has become the focus of package developers worldwide as a means to reduce the size, thickness and cost of chip-scale packages while improving electrical performance. Wafer-level packaging involves the formation of first-level interconnections and package-I/O terminals on the chips before the wafer is diced. As many as 10 approaches to wafer-level packaging have been introduced to meet the needs of a variety of applications. Does this activity represent the ultimate direction of package optimization or just another class of application-specific packaging?

By moving the first-level interconnection process out of the backend of the assembly line, several advantages can be realized. First, handling of individual die is delayed until the end of the assembly process, when the wafer is diced into completed packages. This eliminates the die attach process required for FBGA packages and µBGA® packages.



Second, the sequential bonding to individual bond pads is not done in most cases. This eliminates a large number of the wire bonders usually found on the assembly floor. One exception is Amkor Technology's wsCSP,™ which combines a high-density §ex circuit with conventional wire bonding to create a cost-effective wafer-level process.

Most wafer-level processes, however, are based on either a thin-film deposition process or a mass-bonding process to contact the chip's bond pads. Examples of this include Flip Chip Technologies' Ultra CSP,™ Fujitsu's SuperCSP™ and Tessera's WAVE process. Finally, wafer-level packaging opens the door to wafer-level testing and more potential cost savings.

These advantages are offset by the inherent limitations of chip-size packaging. Because it is, by definition, a fan-in-type CSP, there is a hard limit on the I/O density. If the chip has a large area for the number of I/O, then the package can be made with a pitch that is manageable at the board level. Otherwise, an I/O pitch of 0.5 mm or less will lead to expensive board technology that more than offsets any package cost savings.

This I/O density limitation leads to another limitation: die shrink sensitivity. What happens to the package footprint when the next die shrink occurs? At a minimum, the outer dimensions will shrink. This may or may not have a direct impact on the solder ball pattern. Some memory chips may have enough area to avoid this issue, but it must be considered before committing to wafer-level packaging technology.



Wafer Yield

Another issue to consider is the packaging cost as a function of wafer yield. In most cases, the packaging cost is fixed for a given wafer size and depends on the process complexity and material cost. Therefore, the packaging cost depends on the number of good die per wafer which, in turn, is dependent on die size and wafer yield. For new chip designs, a low semiconductor yield will lead to high packaging costs for a doubled cost penalty. Other factors to consider: solder joint reliability, thermal management and wafer-level test and burn-in.

With these advantages and considerations in mind, wafer-level packaging makes sense for some specific applications.

One area is memory-chip packaging for flash memory, DRAMs and EEPROMs. The relatively large silicon area needed for the memory cells provides enough space for an array of solder balls. Wafer-level packages have been developed for 100 mm2 DRAMs and 50 mm2 §ash chips. Another application area for wafer-level packaging is small devices that measure only 2-3 mm on a side. This includes some analog chips, integrated passive chips, and small EEPROM chips.

Considering the inherent limitations of wafer-level packaging, the technology does not represent the ultimate direction of packaging but yet another CSP solution.

The industry is headed towards more diversification, not a consolidation of options, with diversification driven by optimizations for specific applications, such as optoelectronics.

As such, wafer-level packaging represents an expansion of application-specific packaging. Portable products, low-cost consumer electronics and even some high-performance memories will drive the commercialization of several wafer-level processes.

Mr. Crowley is president of Redpoint Research, a technology analysis and consulting company in the microelectronics packaging field. He can be reached at crowley@redpointresearch.com.