May - June 1999
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Packaging Integrated Passive Devices at the Wafer-Level
Wafer-level packaging is an enabling technology that will help drive widespread adoption of integrated passives and passive-intensive RF subsystems. The technology has an impact beyond providing lower packaging costs, higher product performance and smaller footprints. Wafer-level packaging also allows companies that have a wafer fab to bring packaging inhouse, using their installed equipment base. Figure 1. Intarsia's Conventional and CSP Packages |
At times, these requirements seem to be in con§ict, since increased product functionality may require that more components be placed on a printed circuit board that has already been reduced in size1.
Cellular phones are clearly the most visible "wireless" product and one, in particular, that is expanding in functionality, requiring longer battery life and higher performance at lower costs.
The cell phone market also continues to show aggressive growth forecasts with the global market projected to exceed 200 million units during 1999 and 265 million units by next year2. At these volumes, the products are earning the attention of many suppliers.
 Figure 2. IC and passive content in cell phones (Source: Nokia) |
Many advances have been made in silicon integration for active devices, while passive component integration has lagged far behind.
Passive integration is now becoming a critical factor, especially for wireless products, and wafer-level chip-scale packaging will play an important part in this integration.
Figure 2 illustrates the decrease in ICs in cellular phones from 1994, projected to 2000. The graph also shows the decrease in passive content in cell phones for the same timeframe.
By the year 2000, many observers expect that cellular phones will have less then three ICs in second generation GSM RF, but will still have approximately 100 passives. Those passives represent 95% of the components, 80% of the size, and 70% of the cost.
At the same time, adding modes and bands increases the number of passives in the phone3. If cellular phone suppliers want to decrease the cost and size of a cell phone, they must begin looking at integrating passives.
 Figure 3. 2.45 GHz VCO |
A number of companies are producing IPDs (integrated passive devices) using thin film on silicon, glass or ceramic substrates.
To date, these types of products have not received widespread adoption for a variety of reasons. One of the major barriers to adoption has been the cost of IPDs compared with the cost of using discrete passives. The majority of IPDs sold to date have been packaged using traditional packaging methods (SOIC, QSOP, etc.).
These packages (SOIC, QSOP) represent anywhere from 60% to 80% percent of the total cost of the product. IPD prices have been too high for extensive market adoption, and since 60% to 80% of the cost of IPD's is package related, IPD suppliers have no alternative but to find more cost-effective packaging solutions.
Wafer-level chip-scale packages offer the lowest cost solution for IPD suppliers, and also provide a smaller form factor product with higher performance than alternative packages.
With the possibility of immediately lowering IPD costs using wafer-level CSPs, it will now be possible for IPD suppliers to design for wireless and portable products that will meet designers' cost/performance objectives.
Wafer-Level CSP Adoption
Many IPD companies are adopting a wafer-level CSP approach. This is particularly evident for portable and wireless products where the meaning of CSP goes beyond the designation "chip-scale package" and also stands for the adoption prerequisites of "Cost, Size and Performance."
The two basic approaches to wafer-level CSP for IPDs involve the orientation of the surface of the die in the CSP package after it is soldered to the PC board. One method is to have the die surface facing into the PC board (§ip-chip type). The other approach faces the die away from the PC board (face up).
The "face up" orientation has a number of advantages that make it particularly attractive for a company committed to supplying either IPDs or RF subsystems.
Products that require passive integration, like cellular phones, can take two approaches. The passives can either be integrated into an IPD or a module, such as the 2.45 GHz VCO shown (Figure 3). IPD companies who desire broad involvement in portable wireless products must be able to supply either an IPD or a module.
Intarsia's VCO is an IPD with a varactor diode and transistors mounted on the IPD substrate using chip-on-board technology. The approach currently provides designers with a miniaturized high performance product.
 Figure 4. Wafer-level CSP and subsystems |
The key for Intarsia--and other IPD companies making second generation products„will be to supply this type of RF module in full grid array form, to reduce size further and to mount any active devices without using wire bonds.
The only way to achieve this goal is to adopt a wafer-level CSP strategy that allows for face up orientation.
Using this approach, an IPD company can supply either IPDs in a wafer-level package or an RF subsystem that incorporates CSP devices (transistors, diodes, etc.) stacked on an IPD substrate (Figure 4). The Micro SMT®4 CSP is one technology that can provide this solution (Figures 5 and 6).
The benefits of a face-up CSP package are:
- The die surface is fully protected.
- The backside of a silicon die can be attached to the PC board for heat dissipation or ground (device specific).
- A clear cap can be used for optical applications or trimming.
- The active surface is facing away from the PC board, which can be an advantage in RF applications.
- Using this approach, diodes and transistors can be packaged without the solder balls. These diodes and transistors can then be used for passive-intensive RF subsystems like VCOs.
- Transistors and diodes can be added to this package on the active side (topside) of the IPD.
- Both a solder ball and land grid array option is available.
- Peripheral and full grid packages are available.
 Figure 5. The Micro SMT Package |
As the convergence of portable and wireless products continues, the market will expand rapidly. Competition will drive prices lower and time to market issues will become even more critical. IPD suppliers will be required to turn designs into reality at a faster pace and at lower cost, and wafer-level packaging will be the major enabler for these types of products.
Every company, however, will have to address the full product manufacturing cycle, from design to customer shipment. The primary issues deal with design, fab turn time, packaging time and test-to-ship (Figure 7). The way companies address these four areas will impact how quickly each supplier can respond and react to the changing needs of the customer. Wafer-level CSPs will not only lower costs, but will allow end-product suppliers to shorten their manufacturing cycles.
 Figure 6. Cross-section of Intarsia's CSP structure |
The design issues are not trivial in RF passives. To reduce turnaround time for customers, IPD manufacturers will have to provide tools that will enable their customers to design for their needs internally before contacting the IPD supplier.
This will allow customers to try different approaches to meet their needs in realtime. These tools must be capable of predicting results that will allow "first-time functionality" of designs. If the customer has to depend on the IPD company to model and simulate designs, then the design time will be increased.
The added communication time between supplier and customer will ultimately impact time-to-market. If the tools used are not accurate in their predictive capability, then designs will have to be iterative, resulting in higher IPD costs.
Intarsia is supplying design kits based on our process to customers, which will shorten the design time for products. The next phase of the manufacturing cycle is the fabrication of the product in the factory.
| Yield Comparison in Die per Wafer |
||
| Substrate Size |
Die per Wafer* |
Area Factor |
| 100 mm Wafer | 1,261 | 18x |
| 150 mm Wafer | 3,181 | 8x |
| Panel** | 27,083 | 1x |
| * Die Size: 1206 (120 x 60 mils) ** Panel Size: 350 mm x 400 mm |
||
As mentioned, 60% to 80% of the cost of IPDs produced in conventional packages, like QSOPs, are the cost of the package itself.
This has been one of the major barriers to widespread adoption of IPDs. Wafer-level packaging can lower that cost dramatically. The semiconductor paradigm has always demonstrated that a larger substrate will provide a path to lower costs. There has not been a strong motivation for IPD suppliers to move from 100 mm to 150 mm wafers since the market was small and the reduction in silicon or fab costs would only affect 20% to 40% of the cost at best.
The packaging cost had to be addressed to make the market opportunities improve. With wafer-level packaging now promising a big advantage for IPD suppliers because of cost reduction, a move to larger wafers can be cost effective.
IPDs do not require submicron processes for fabrication. As a result, fabs that are no longer suitable for ICs can be used for IPD fabrication. Another area being watched by Intarsia and other companies is the use of large area panel processing to reduce cost.
Figure 8 compares the size of a 350 mm x 400 mm large-area panel with 100 mm and 125 mm wafers. The economy of scale achieved using a large area panel is dramatic, as noted in the table, when compared to 100 and 150 mm wafers.
The choice of glass as a substrate provides two advantages. The first is its low cost coupled with its availability in a large panel format. The second advantage glass offers is its high resistivity, low loss, low dielectric constant attributes, which are suited to higher frequencies.
Typical values for the material in use are Er=5.7 tan £<-0.001. The large area panel process would not be a viable solution for IPDs if the die, after coming out of the fab, were then sent out for packaging using traditional methods.
Large-area panel fabrication combined with wafer- or substrate-level CSP packaging offers lower costs than can be realized for high performance IPDs on 100 and 150 mm wafers.
 Figure 7. Design through shipping flow for RF IPD |
Wafer-level packaging is an extension of the fabrication process. Because of that, companies that have fabs can also package their own products.
An additional capital outlay of about 10% is required, but those costs are easily recouped. An IPD company can use the same equipment to fabricate and package the wafer.
Different skill sets are not needed for operator or maintenance personnel, which means better utilization of personnel and lower costs for the company. This also enables the fabricator to control its own turnaround time from fab to package—a great advantage when priority runs occur. No time is lost in transit to a packaging company, which is a great advantage for an IPD company.
 Figure 8. Large-area glass panel compared to 100 and 150 mm wafers |
One of the promises of wafer-level packaging has always been the goal of fully testing products while they are still in wafer form. This is now one of the major issues facing any company adopting wafer-level packaging.
The ability to test at the wafer level has been demonstrated by a number of companies. However, the capacity to "inexpensively" test IPDs in volume has not been demonstrated to date.
The test infrastructure enabling low-cost testing had not been developed until very recently. A number of companies have the ability to sample test IPD products in CSPs for customers, but are not set up to handle large volumes.
That infrastructure first developed for BGAs and interposer-type CSPs and has lately grown to encompass wafer-level packages. A Micro Component Technology (MCT) Tapestry system, recently purchased by Intarsia, will fully test wafer-level CSPs while they are singulated and fully isolated but held in wafer form. Testing in wafer form will not only be quicker, it will also be less expensive.
 Figure 9. MCT's Tapestry test handler for wafer-level CSPs |
Intarsia has seen the upside and has adopted wafer-level chip-scale packaging for its line of integrated passives and RF subsystems. We have also adopted a technology that can be used on both its glass panel and wafer line.
The face-up approach offers an additional benefit because it will allow us to package transistors and diodes without the use of wire bonds for assembly on RF subsystem modules. Wafer-level packaging is expected to allow companies to provide faster turn time to customers since the entire manufacturing process from fab to tape & reel is done while the product is in wafer form.
References
- E. Logan et al., "Advanced Packaging of Integrated Passive Devices for RF Applications," Proc. IEEE Radio and Wireless Conference, 1998, Colorado Springs, pp. 289-292.
- Ericsson Press Announcement, "Ericsson Announces New Mobile Phone Forecast," August 27, 1998.
- E. Kuisma, "Challenges and Opportunities for Handset Design," International Wireless Packaging Consortium Meeting, October 1998, Helsinki.
- Trademark of Chip Scale International.