Multimode Compliance Interconnect Provides High Speed CSP Test and Burn-In

Figure 1. Illustration of general Multimode Compliance Configuration which can be used for high-speed test, burn-in, programming, prototype, etc.

The Socket Designer's View

The view from the socket designer's perspective is quite different from that of the package designer or CSP end-user. One might think that a CSP is just a small BGA, with BGA fabrication techniques simply scaled to a finer level. This is not the case in most instances. For all practical purposes, any device with a terminal pitch smaller than 1.0 mm might be considered a CSP from a socket or connector perspective. As time progresses, even devices with a larger pitch will migrate to the CSP-level pitches of 0.8 mm and 0.5 mm. The socket manufacturer does not define a CSP as 1.2X the die size, although that is the generally accepted definition of this format. In general, the most important feature to be considered is terminal pitch and solder ball size. This definition basically determines the target that must be contacted and the distance between targets. Significant performance or cost concessions have been made in some areas to merely provide a solution at 0.75/0.8 mm pitch. Below this pitch, traditional techniques have proven less than successful.

Design Challenges

The interconnect designer must create a contact member sufficiently small to prevent shorting, yet robust enough to be physically assembled or last more than one insertion without destroying the solder balls. To date, socket companies have operated in a relatively industrial manner, where low cost of introduction has been enjoyed.

CSP development forces these companies to enter into unfamiliar territory with a hopefully educated bet on which technology will win in the end. The days of producing a product determined by the supplier and offered to the market seem to be over. The market is determining what products must be provided, and demands innovation to support them.

CSP size and configuration will constantly be changing from device to device, and producer to producer, impacting socket design and production. This type of situation may be difficult to manage, but in the end it drives innovation. The results of a technology study have driven the development of technology (example shown in Figure 1) to support the needs of the evolving market, rather than attempting to force the market to conform to the needs of the socket producers.

Figure 2. A common standard alignment frame used to accomodate a wide variety of suspended contact sets or devices.

Interconnect Development

A family of connector and socket products has been established to meet the emerging needs of CSPs. The products are configured to connect a wide variety of packages down to fine pitches with a unique contacting methodology that relies on multiple modes of compliance. In general, a basic group of socket frames accepts a suspended contact set containing the appropriate contact or device configuration. When the suspended contact set reaches the end of its life, or a different device is to be socketed, the contact set is simply removed and replaced with another appropriate contact set. The main component subject to failure or change is easily maintained or configured to meet the needs of the application, while the use of common components increases volume usage and reduces overall cost.

In addition, the entire product family is configured to mate with other Gryphics Removable Chip Module (RCM) products. A great many functions can be incorporated into the mating RCM beyond simple redistribution (Figure 3). As test parameters and tester electronics become increasingly complex and constantly in need of adaptation to next generation products, many of these functions can be provided on devices loaded into the RCM interface and removed and replaced as desired.

Considerations

As CSP users evaluate the entire process required for producing their devices, they must consider several factors that will impact the implementation. It is in the socket producer's best interest, as well as the producer's responsibility to help the customer determine the parameters that are most important to the application. The general factors considered to determine the Multimode Compliance product families apply to both test and burn-in sockets, but differ in priority. They are:

• Pitch Capability
• Cost
• Tooling
• Lead Time
• Mechanical Life/ Maintenance
• Solder Ball Deformation
• Impact of Die Size
• Non-Recurring Engineering Charges
• UUT/Burn-in Circuit Board Complexity/Cost
• Electrical Performance

Figure 3. Redistribution option allows high speed interconnect and I/O fanout to relax PC board manufacturing demands.

Functional Test Vs. Burn-In

When considering the functional requirements of test compared to burn-in, there are several commonalties as well as dramatic differences. One common thread is the main driver for the key failure mechanism--solder build-up or contamination. Inevitably, if the socket is used properly to eliminate premature failure due to mechanical over-compression, solder transfer results in a high resistance deposit. The other common factor between both types is the importance of cost. Overall cost of use is a major focal point of all users. Traditionally, burn-in sockets have been through hole types, with a few companies offering limited surface mount options. The contacts used in these sockets are large, long and are not capable of providing high signal integrity interconnects. As a result, burn-in operations have not incorporated functional test parameters.

These sockets are used in medium to large volumes, and are very cost sensitive. The main driver for burn-in socket design--beyond acceptable function--is cost. Several companies offer 0.75 mm socket products, and each offers benefits and limitations.

Beyond this pitch level, few technologies have come forward. At these pitch levels, solder ball deformation is a critical parameter. Extended exposure to heat with force applied tends to alter solder ball shape. The contact shown in Figure 4 was developed to provide a high-speed contact while supporting the solder ball with a cup or dimple shape, reducing or eliminating ball deformation.

High performance test sockets are typically lower volume units with expectations of long mechanical life and low parasitic signal properties. This higher level of performance usually demands a higher price tag, as well. These sockets are made with low volume processes, and typically have been produced as custom units with little or no tooling involved.

Figure 4. SEM of one style of multimode compliance contact member.

Performance Parameters Pitch Capability - Ranking 1

For each type of technology and application, pitch capability was given the highest ranking. This may seem academic, but many technologies fall short when applied to CSP devices.

Cost - Ranking 2

For each application and type of technology, cost was placed second in importance. Cost is always an important issue, tempered with reliability and function.

Tooling

Tooling cost is a major factor, particularly in the burn-in arena. To achieve the appropriate cost points and volume capabilities, mold and stamping tooling must be produced. This is one of the major issues impacting CSP burn-in. A lack of standards and the race to be the "CSP of the Week" is responsible for the many different styles and form factors. Test sockets usually do not require tooling due to the low volume requirements.

Lead Time

Lead time for burn-in sockets is largely dependent on tooling lead time. If the socket components are already tooled, this is not an issue. As CSPs, or fine pitch BGAs, progress with shorter times to market, lead time can be critical.

Test socket lead times are in general similar between technologies, with a few exceptions. The main process used to produce these lower volume units, CNC machining, is specialized, but readily available.

Mechanical Life

Mechanical life is important in all applications, with the level of tolerance and expectation differing from test to burn-in and cost-point to cost-point.

Burn-in sockets have typically been expected to fail with far fewer insertions than high performance sockets and are removed and replaced as entire units. To date, socket savers or interposers are used to allow for the sockets to be removed without reflow of soldered pins.

This is especially critical for CSP applications, where burn-in boards are very difficult to produce and expensive at the pitch levels involved. Again, mechanical relaxation or fatigue is one factor for failure along with solder deposits oxidizing and causing high resistance or opens. Typically, the pins in traditional sockets are not individually replaceable, and the entire unit is discarded as a consumable item.

Test sockets are usually higher performance units, where many thousands of insertions can be expected. Again, the cost of test or insertion is important, as well as the ability to minimize test system downtime. Typically, test socket designers try to allow for individual contact replacement or socket refurbishment. The procedure for repair, the mean time between repair, the cost and availability of replacement parts, and success in life extension are all to be considered.

Solder Ball Deformation

Solder ball deformation is important for both styles of sockets. One issue that has been highly publicized is the effect of solder ball deformation on final assembly re§ow.

Several studies have shown that the volume and application of solder is critical in the reliability of the assembled joint. Many users in the BGA area test and burn-in without solder balls, in an LGA format, to avoid the issue completely. Solder ball attach processes for BGA production have proven reliable enough to allow for vision scanning or final inspection. This may or may not be a viable approach for CSP devices, particularly in the case of tape or flex-circuit based packages which may be damaged or punctured. In the case of burn-in sockets, many of the tweezer styles in use today would have nothing to grab onto if the balls were not present. Variations in ball diameter also impact the efficiency of contact, and may drive a new contact geometry altogether, increasing costs.

Impact of Die Size

Alterations in the die size, as mentioned earlier, is of significance to the burn-in socket producer. Gross package alignment is usually done by keying on the body of the device. In the case where the socket must be actuated in order to bring the contacts to bear, such as with tweezer style, if the balls are not near the appropriate place to begin with, the mechanism is at risk. Changes in die size have usually generated a special insert or modification, which again increases cost. At finer CSP pitches, the issue is heightened.

Traditional test sockets are not nearly as sensitive to die size changes, since the volume is low and the machining process can easily accommodate minor alterations. Since the costs of these sockets are so much higher, 10-30x, the cost impact is minimal.

Non-Recurring Engineering Charges

NRE charges are common in many areas, and are accepted to a certain degree, but some technologies are more adaptable than others.

UUT/Burn-in Circuit Board

At CSP levels, burn-in boards and high performance load boards are difficult and expensive. Some technologies have a greater impact on board costs than others. This must be considered in overall cost of use and lead time. At finer pitches, the board makers often must produce several pieces to yield only one functioning board, if they can produce them at all.

Electrical Performance

Electrical performance has been well defined between test and burn-in. Until recently, signal integrity has not been as critical in burn-in sockets, or burn-in sockets were not capable of high performance, so they are not expected to provide high signal integrity. Increased interest in functional high-speed test at burn-in was a major consideration in Gryphics' product development.

Test sockets, by their nature, are expected to have higher performance. Some technologies are better than others from an integrity and contact inductance standpoint.

Results of Evaluation and Comparison

The results of this evaluation show that there is a definite gap between the needs of the CSP infrastructure and the technology which traditional burn-in sockets are capable of providing. The major impacts of pitch capability, tooling, leadtime, insertion count and solder ball deformation identify specific design parameters to address.

Essentially, the market requires burn-in sockets that can reach CSP pitches, are low cost, do not require thousands of dollars of tooling or months to produce. This trickles down to a family of products that is less sensitive to die or package size changes and minor variations of ball size. Once again, the impact of solder ball deformation is increasingly important as pitches shrink.

This evaluation also shows that there is a gap between what customers want and what test socket producers are providing. The industry requires a test socket with high signal integrity, sufficient mechanical life and lower cost.

Figure 5. A Multimode Compliance, self-actuating ZIF connector for high speed connection to edge cards.

Technology Voids

The results of this analysis identify several technology voids. The mere fact that sockets are split into burn-in and test categories indicates a major technical void. To date, there has been no technology that is appropriate for use as both a burn-in solution and a high performance test socket. Semiconductor manufacturers, packaging producers and contract manufacturers have been forced to investigate and implement separate solutions to ship parts. This issue adds additional cost and complicates the entire process. There are low cost, low-performance sockets and high cost high-performance sockets. There has been nothing available as a compromise between those extremes, until the Multimode Compliance product development.

As individual CSPs migrate to wafer-level packaging options, the issue becomes compounded. The major devices slated for CSP applications are prime candidates for functional test at burn-in and even wafer-level test and burn-in. Many companies are also investigating the merits of multi-site CSP test while the CSPs are still in strips or carriers. Again, the issues related to a single package interface are compounded when multiple devices must be contacted in parallel.

Figure 6. One syle of ZIF actuation.

Applications

As with any product development effort aimed at a specific group of applications, it is easy to remain focussed only on the specific application at hand. In the case of CSP interfacing, it is necessary to look beyond connecting an individual package. When an overall system use approach is employed, the next level of assembly must be considered. Many CSP applications eventually are assembled to a PC card, substrate or module.

The final assemblies often benefit or rely on the increased performance of the smaller packages. This increase in performance can be lost or defeated by testing or connecting the assembly with high inductance or low insertion life connectors. A development effort driven by an industry-leading semiconductor producer, in conjunction with GTE-ERS Engineering, Catalyst Enterprises, and Gryphics Inc. has resulted in an extension of the Multimode Compliance technology to support high performance, low maintenance testing of PC board assemblies and cards (See Figures 5-7).

Figure 7. Maintenance is easy: Remove suspended contact set, replace and continue operation with minimal downtime.

Conclusion

The rapid adoption of CSP packaging is an exciting and critical evolution in the electronics industry. Semiconductor companies are constantly striving to increase their competitive advantages and profitability. With front end fab capital expenditures draining more and more resources, backend packaging and test departments are faced with decreasing budgets and constant demands to reduce cost. In addition, companies are striving to extend the life of existing product offerings, usually with concessions in pricing. The recent events in the DRAM industry are a prime example of how price per performance pressures can unseat an industry and entire economies.

Test and burn-in are being constantly evaluated for their need or value, but the need to evaluate the packaged devices prior to use is still mainstream. As new technologies enter the semiconductor manufacturing process, such as copper interconnects and other technical advancements, the need for high speed, low parasitic interconnects at all levels becomes increasingly important.

Devices with hundreds and thousands of I/O spaced at tight pitches are here today, and will increase in popularity. The Practical implementation of test and burn-in to be successful must consider the entire process from front end to end-system use. The Multimode Compliance interconnect product families are intended to meet the needs of increasing speeds of modules, system busses, CPUs and next generation architectures cost effectively.

This paper was adapted from a presentation by the author at the Pan Pacific Microelectronics Symposium, SMTA, February 1999.

Further Reading

1. T. Di Stefano, "Microelectronics Packaging Into the 21st Century" Symposium Proceedings, December 1996.
2. C. Lassen, "Pivotal Packaging Technologies for Tomorrow's Products," Ibid.
3. C. Chiu and N. Lee, "Options and Concerns of BGA Solder Bumping," Chip Scale Review, December 1997.
4. P. Waurzyniak "Emerging Technologies to Boost Industry Growth," Electronic Buyers' News, Jan. 5, 1998.
5. J. Hwang, "Will Flip Chip or Chip-Scale Packages Take Over," SMT, October 1997.
6. R. Lanzone, "Ceramic CSP, Options for a Low-Cost, High Density Technology," Advanced Packaging, September/October 1997.
7. S. Merchant, "Successful Implementation of PCMCIA Assembly," SMT, March 1998.
8. C. Windsor and T. Chung, "Reworking Chip-Scale Packages," SMI Chipscale Packaging Symposium, September 1997.
9. S. Raissi, "Dr. Raissi on Chip-Scale Package Testing," Chip Scale Review, May/June 1998.
10. T. Chung et al., "Updates on Worldwide Chip-Scale Packaging," SMI Chipscale Packaging Symposium, September 1997.
11. J. Forster, "Socket Challenges for Chip-Scale Packages," Chip Scale Review, May/June 1998.
12. B. Brost, "Good Contact Design Improves Test Performance in BGA/CSP Applications," Proc. Of Chip Scale International, May 1998.
13. D. Pfaff, "Burn-in Socket Requirements for CSP," Proc. Chip Scale International, May, 1998.
14. R. Crowley, "Socket Developments for CSP and FBGA Devices," Chip Scale Review, May, 1998.