| An Expert Looks at the
Issues |
Steve Anderson on IC Package Assembly
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Mr. Anderson is Senior Vice President
for corporate product marketing at Amkor Technology Inc.,
the largest IC packaging foundry in the world. He has more
than 20 years experience in the package assembly industry
and has served in executive posts with Texas Instruments,
as well as Amkor. Mr. Anderson is based in Amkor's operations
center in Phoenix, Ariz. He is on the Chip Scale Review Editorial
Advisory Board and is the author of an article on IC packaging
that appears in this issue. [sande@amkor.com]
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Will
the explosion in telecom add new players to the ranks of IC assemblers-or
result in consolidation?
According to market research firms such as IC
Insights and Dataquest, the explosion in telecom is resulting in
consolidation of suppliers for key components like DSPs as well
as the addition of new suppliers for RF components-which are especially
critical for the huge growth of wireless devices and applications.
The market entry of new device manufacturers,
who specialize in large niche markets, is increasing the need for
more specialized IC packaging and the requirement for more engineering
assistance from the packaging foundries. The major IC assembly companies
today are going public to ensure better access to the financial
markets that will help fuel their growth as they support the outsourcing
trend. We also could see some new IC assemblers involved in the
manufacture of modules targeted for portable products.
Do
you anticipate much impact from lead-free movements?
The impact to IC assemblers will depend on what
their customers-the IC manufacturers and the equipment makers-require.
It is likely that Japan will be the first to legislate the requirement
that equipment manufacturers recover lead in obsolete products,
as part of a new household electric appliance recycling law scheduled
to go into effect next year.
The impact to assemblers will likely require
that packages be made more robust to withstand a higher SMT peak
soldering temperature of 260oC. This change is forcing
a review of improved epoxies that will reduce the chance of "popcorning"
and cracking.
Additionally, BGA and CSP substrates may change
to eliminate halogens and other toxic materials. Assemblers may
have to requalify existing BGA and CSP packages with these modified
substrates. Finally, the lead plating or ball composition and solder
paste employed to attach the IC packages to the system board will
have to be requalified and re-tested with materials that eliminate
lead.
How
dense can packages become and still employ wire bonding?
The limits of wire bonding are continually pushed
with each new die lithography reduction and resulting die shrink
or increase in die interconnection density. Bonding pad pitch or
spacing is continuing to decrease and should reach 25-30 µm at the
0.10 µm lithography technology node.
It appears that most wire bonding equipment
suppliers will need fine-pitch capability at the proper time. Performance
issues, particularly for wireless and high-speed applications, is
forcing a segment of products into flip-chip to achieve the shorter
interconnection path. As a result of the increased use of laser
via drilling, we expect to see BGA and CSP substrates that are much
denser. Laser drilling should also extend the life of wire-bonded
packages.
It
seems that every packaging foundry wants to offer flip-chip assembly.
What are the costs of entrance?
The major costs of providing flip-chip assembly
are high-volume bumping and redistribution manufacturing capability
tightly coupled to IC dense substrate design capability and tools.
Additionally, accurate manufacturing placement
and underfill capability (especially for non-eutectic joints) is
needed. Finally-and significantly, highly trained, experienced personnel
are mandatory. The ability to scale up for large volume while managing
cost reductions is imperative for this technology to become effective
in an increasingly consumer-driven market.
According to Jan Vardeman of TechSearch International,
"If you're talking about flip-chip-on-board (FCOB), the major barrier
is the known-good die issue. Because the bare die attached to the
PC board must be underfilled, and commercial underfills are not
available, there is also a concern about repairability," Vardeman
maintains.
Flip-chip-in-package (FCIP) is in widespread
use, both for high I/O products, such as microprocessor, ASICS and
DSPs and for low-end products where form factor drives FCIP use,
Vardeman notes.
Do
you expect the rankings of IC packaging foundries to be the same
two years from now?
The rankings for 2000 are very similar for Amkor,
with a market share of >25% with the next market share grouping
of 1% to 15%. Based on the latest report from Electronic
Trend Publications, it appears that the rankings have not dramatically
changed. The aggressive advent of newer technology may pose challenges
to those assemblers that are not able to finance and hire the experts
necessary for the packaging customization we see appearing today.
Onshore
assembly, with few exceptions, has not been successful. Is it still
viable?
Offshore assembly is so entrenched with such an established
infrastructure and wage structure that it is difficult for U.S.-based
assembly firms to be competitive. There are certainly opportunities
for small, rapid-turn prototyping centers that can test new technologies
to resolve customer issues before large-scale volumes are required.
Also, as the system-in-package or module direction becomes clear,
there may be opportunities to perform low-volume quickturn assembly.
What
is the major driver for new IC assembly equipment?
The major driver is flip-chip packaging, for both
attachment, underfill, basic bumping and redistribution processing
lines. We will see 300 mm wafer sizes driving a new generation of
wafer saws, backgrinding equipment, wafer probing and mapping handlers,
die attach systems and wire and flip-chip bonders. Those assemblers
that also provide wafer bumping will have to retrofit or add new
lines to handle 300 mm diameter wafers.
How
will the growth of wafer-level packaging affect IC assemblers?
Last year, only 5.5% of all CSP production
was wafer-level packaging (WLP). By 2002, it is expected to drop
to 2%. Nevertheless, it appears to be too early to tell what
long-term impact WLP will have on the IC assembly model. We see
WLP as a natural extension to the CSPs we are now producing, albeit
with different materials. As wafer-bumping capability develops at
the IC assemblers, WLP will be another format available to customers.
In the future, WLP will be produced on the bumping
line and will have access to the same wafer testing and mapping
capabilities that will exist for flip-chip packaging. Many IC assemblers
will likely see this as another technology that can produce standalone
packages or be integrated into system-in-package or modules.
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