What is flip-chip (FC) interconnect technology? Generally speaking, we can define it as the active side of the silicon device facing the substrate, interconnected by solder joints, TAB, stud bond, isotropic/ anisotropic conductive adhesives or just adhesives (in paste or film form) between the IC and substrate. Based on this definition, the first flip-chip technology was practiced in the 1950s by Bell Labs at Western Electric's manufacturing plants (then AT&T, now Lucent Technologies). Bell Labs called its peripheral flip-chip interconnect structures "beam leads," which were formed on a wafer-form, batch process. These beam-leaded devices were gang-bonded by thermocompression to a ceramic hybrid integrated circuit (HIC) for telephone circuit packs that were used in most telephone central office switching systems. (Today HICs route Internet services.) RTV silicone elastomers have been employed to underfill these small beam-leaded devices for corrosion protection for many years. Billions of these devices have been made in the past four decades. Their reliability is unquestioned by most of the telephone companies using them. However, Totta and Miller developed important area-array, flip-chip technology at IBM in the early 1960s. They used copper and high lead (95/5 Pb/Sn) solder balls for their flip-chip interconnection method, which is known as C4 (controlled collapse chip connection). These flip-chip devices are mounted on an expansive ceramic substrate, where TCE mismatch is less critical than in the Bell Labs' work. The reliability of these flip-chip devices is superior to beam lead, due to their under-bump metallization (UBM) and improved thermo-mechanical attributes. In the mid-1980s, Hitachi reported that the ceramic flip-chip module's fatigue lifecycle can be further enhanced by underfilling the ceramic flip-chip structure with epoxy adhesive. Due to the high cost of the ceramic substrate, however, this technology was not widely practiced until the late 1980s, when it was implemented by Tsukada of IBM's Yasu Lab in Japan. Tsukada reported the successful implementation of flip-chip on FR-4. His work was the first to demonstrate the manufacture of a high performance, flip-chip device on a low-cost PWB substrate. Epoxy underfills with TCEs that match the solder joints' expansiveness are the key to enhancing the cycle fatigue life performance. The epoxy underfill couples the silicon IC and the organic substrate and reduces the TCE mismatch between the flip-chip IC (TCE˜2.5ppm) to the organic board (TCE˜18 ppm). As a result, the shear stress is evenly distributed to all solder joints, rather than being concentrated on the outer and farther joints.
There are two types of flip-chip technologies now employed. First is the conventional (capillary) type (Figure 1). Second is the no-flow (compressive flow) type, which was first demonstrated and reported on by Georgia Tech's Packaging Research Center (Figure 2). The no-flow type can result in tremendous cost savings.
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