The explosion in demand for chip-scale packaging as a suitable technology to meet the tight space requirements of wireless products, and new efforts to integrate optical and mechanical microdevices with conventional semiconductor electronics characterize the status of packaging today. Interconnect Translation Shrinking die lithography implies tighter metal pitches-including the pitch between bond pads. The latter puts pressure on packaging engineers to develop higher density packages that increasingly take advantage of flip-chip technologies. Why higher density? Because second-level interconnects-system board-pad pitches-are not shrinking as rapidly as IC bond-pad pitches. At 0.5 µm, the typical die bond-pad pitch was 100-120 µm; at 0.35 µm, it was 80-100 µm. At 0.25 µm, it was 70-80 µm for wire-bonded packages and 250 µm for flip-chip. Today, at 0.18 µm, pad pitch on die can be as tight as 60 µm for wire bonding, and 200 µm for flip-chip packages. The IC packaging industry's response to these shrinking pitches has been to develop a variety of area-array, enhanced leadframe and even stacked packages. Externally, area-array packages range from 1.0-1.27 mm for the generic PBGA, down to 0.5 mm for Amkor's FleXBGA and ChipArray and 0.75 mm for Tessera's µBGA package . Flip-chip in package (FCIP) offers a pathway to both chip-scale packaging and to interconnect levels beyond 700 I/O with power improvement. A flip-chip PBGA can be enhanced for thermal and electrical performance by bonding the chip to a metal lid with a thermal adhesive. Many existing and evolving BGA packages and CSPs, which now support wire bonding will incorporate flip-chip technology in the future. FCIP technology can effect the required translation between very dense IC connections and the cost of second-level system board connections by minimizing the area of substrate needed. Prismark Partners is predicting 1.7 billion FCIP units in 20031. A reliable supply of laminates is a key element to making FCIP practical. A four-layer substrate is needed for 700 balls. More I/Os require even more layers. The infrastructure to provide the organic substrates needed to address second-level issues has been developing to meet this need, although to make flip-chip BGAs truly economical, their cost must decline further-something that appears to be taking place. Recent data from Prismark Partners shows that the mean price of build-up multilayer laminates is converging with the cost of more conventional laminate materials2. An important difference between a conventional flip-chip PBGA and a flip-chip CSP is that the CSP is assembled, packaged and tested in a matrix and then singulated. This is similar to the difference between the wire-bonded TapeArray and FleXBGA packages. Die lithography reduction is also gradually driving interconnect to direct-attach flip-chip in new designs. While used in watches and displays for a number of years, flip-chip technology is starting to see wider use, first in high leadcount packages and next in high-performance packages with lower lead counts. System-in-a-Package and MEMS Another trend is the use of high-density interconnect technology to place multiple die and passives inside the same module to create a system-in-a-package. The SiP approach to high integration is complementary to "system-on-a-chip" (SoC). Where SoC is particularly appropriate for high-volume applications, SiP is most appropriate for mixed technologies, lower volumes and the integration of passives. Both approaches provide a known-good component solution, and both provide pitch translation between chips and system boards. By placing die and passives as close to each other as possible, SiP minimizes package parasitics. Mixing semiconductor technologies and passives in SiPs is leading to the incorporation of optical and mechanical elements. Today, micro-electronic mechanical systems (MEMS) find application in such products as inkjet print heads, automotive airbag deployment sensors and implantable medicine dispensers. Assembly Practices Currently, however, there is very little in the way of inexpensive, high-volume packaging for MEMS. In some cases, MEMS will cause us to re-think systems assembly practices. For example, the trend has long been away from through-hole leaded packages. For electro-optical MEMS, leaded packages provide a mechanism for focus adjustments, however. Major unresolved issues include the question of whether conventional mechanical theory applies to very tiny structures where electrostatic forces are more significant than friction. Moreover, we don't yet fully understand how to control material properties. No doubt other issues will arise as packaging, electronics, optical and MEMS components interact. Summary Future generations of packages will have to deal, first of all, with the sheer I/O density made inevitable by shrinking die lithography, as well as with the increased speeds of devices built on advanced processes. This is leading to finer wire bond pitches and FCIP assembly. Multiple-layer micro-via laminate substrates will also be essential. In addition, the system-in-a-package - with system-on-a-chip IC densities plus mixed process technologies for active devices (some perhaps stacked, to minimize package footprint), in-package passives and package inserts for better thermal properties (or as ground planes), will become a growing segment of the packaging business. Finally, add the integration of micron-scale mechanical and optical components-and the entirely different packaging challenges they bring-such as transparency and electrostatic issues-and we find ourselves facing a very exciting and interesting new decade. References
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