An Independent Journal Dedicated to the Advancement of Chip - Scale Electronics July - August 2000 Email the editor

By David Francis and Linda Jardine, Contributing Editors Patent Number: 6,050,832 Assignee: Fujitsu Ltd. Inventors: Lee, et al. Title: Chip and Board Stress Relief Interposer

Certain families of die types are increasing in both physical size and in the amount of power that they dissipate.

These problems are accompanied by an increasing frequency of power cycling and many more I/O.

Flip-chip is the most obvious solution to the increased I/O issue, but mounting a flip-chip device to a suitable substrate may cause high levels of stress in the solder joints, leading to early failure.

The reliability is further reduced with increasing TCE mismatch between the substrate and the silicon.

Silicon has a TCE of 2.5-3 ppm, while ceramic has a TCE of 7-11 ppm. An epoxy glass laminate substrate possesses a TCE of 16-18 ppm.

If a 2 cm x 2 cm chip increases by 60^oC in operation, the relative increase in linear dimension for these materials in their unrestrained state is about 3 microns for silicon, 8 microns for ceramic and 20 microns for PWBs.

Note that the differential expansion is too great for most joining materials.

Interposers

One solution to this problem is to put some type of an intermediate layer (or interposer) between the chip and the substrate that can absorb some of this differential stress.

Various interposer designs have been developed in which the TCE of the interposer has been adjusted to match that of the substrate, or the chip or be somewhere between the two.

A problem with many of these interposer designs is that the interposer material must be thick enough to be processed using standard semiconductor fabrication techniques.

This thickness is sufficient to make the interposer relatively inelastic.

In addition, the metal conductors and via connections further reduce the ability of the interposer to flex when stress increases.

Certain metals such as nickel, which is frequently used as a barrier layer, have very low ductility, and this acts to further restrain movement.

The result is that most current interposer designs are too rigid to provide the level of stress relief required by new generations of devices.

Top surface of interposer showing stress-relief slots

The figure shows one interposer design that offers a substantial reduction in solder joint stress.

In the approach shown, slots, holes or other approaches can be used to substantially decouple the interconnect area from the main part of the interposer.

The large pad on the top surface connects to the bump on the IC. It is located remote from the via that connects to the pad on the bottom side of the interposer. The bottom pad connects to the pad on the substrate.

After the device is mounted onto the substrate with the interposer, repeated power and temperature cycles will eventually cause the corner connection to tear, resulting in a very low-stress, flap-like interconnection between substrate and IC.

This design effectively decouples the interconnect region from the higher stress main interposer area, while allowing for high manufacturing yield.

Minimum Stress

The flap design allows relative movement of the substrate with minimum stress on the solder joints involved. The use of a flap design permits 15 microns or more lateral displacement with very low stress.

The patent describes a number of different designs for creating low-stress interposer designs. Both BCB and polyimide are suitable interposer materials.