Wafer-level packaging began, as the name implies, as the packaging of integrated circuits on the wafer before dicing it into chips. The rationale is transparent: At the wafer level, you reduce backend costs by packaging chips in a batch, thereby simplifying the process. Rather than performing one-at-a-time mechanical processes for handling and wire bonding chips, we can now process tens of thousands of bonds on a wafer at one time. Wafer-level packaging promises to do for packaging what the integrated circuit did for the transistor half a century ago! New Functionality This story does not end with cost reduction. As was the case with integrated circuits, wafer-level packaging allows us to add completely new functionality to the chip. The strategic allure of wafer-level packaging is the capability of integrating additional interconnects, passives, optical links and as yet unforeseen elements into the final packaged device. It is difficult to project the details, but this capability will find applications that will add new chapters to the semiconductor saga. Wafer stacking is emerging as a technology with the potential to impact the industry greatly. This new dimension to wafer-level packaging has not gone unnoticed. Several semiconductor industry giants are developing stacked chips as a way to produce DRAM or higher density and performance at lower cost. These programs go well beyond 3-D packaging of memory chips - that has been relegated to the sidelines. Chip Redesign Designers are finding ways to redesign DRAM chips by employing wafer stacking to integrate functions that are distributed across a chip stack in new ways. Links from one chip to another have minimum capacitance and inductance compared to conventional packaging. Chip-to-chip communication in the stack is greatly simplified. Off-chip drivers for interchip communications now look more like on-chip circuitry. Large and power hungry CMOS drivers are not needed for these links. Lower cost nMOS may be adequate for many of the wafers in the stack, where CMOS can be used on only those layers that require I/O from the stack. We could go on about ways to rearrange memory arrays to make use of 3-D connectivity. Lower power dissipation of the nMOS layers allows stacking more nMOS layers without exceeding thermal limits. The possibilities are enticing, and hard to predict beyond the first few steps. But that's what makes the field exhilarating. Wafer stacking is not without challenges. Because the rewards are so great, you can be sure that teams of engineers are working to break though the roadblocks. Assembling chips in a wafer stack presents testing and yield problems. Is a stack of chips yieldable? How do we connect front-to-back? Must we thin the wafer to a membrane? How do we do test and repair? What about wafer-level burn-in? Is it necessary? What about logistics? These and other questions are being addressed, and they must be answered before wafer stacking becomes a reality. DRAM products using wafer stacking are a long way from a market reality, but the development in this activity bears careful watching. Without question, wafer stacking is one more in an expanding list of wafer-level packaging technologies that go beyond simply "packaging."
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