Cost, performance and form factor have become the key drivers in selecting between wire bonding and flip-chip bonding as the "preferred" IC interconnecting method. Applications such as cellular telecommunications and wearable portable consumer electronics often require the use of flip-chip packaging for its small form factor and, in some cases, high speed. In other cases, typically with I/Os in the range of 100-600, the existing infrastructure, flexibility and materials/substrate costs of wire bonding provide dominant advantages. Further segmentation is provided by the emergence of several intermediate hybrid interconnect alternatives, such as stud/ball bumping1, gold and aluminum ribbon wedge bonding, under-bump metalization (UBM) that can be both bumped and wire bonded, wafer-level packages (WLP) with and without underfill, Direct-Chip Attach (DCA) or CSP packaging. Wire-bonded CSPs take advantage of the existing infrastructure to produce packages with near-chip-size form factors2. These alternatives currently are less widely used and will not be addressed in detail in this article. Figure 1 summarizes the technology choices and associated design issues that typically determine packaging strategy3. Cost underlies all initial package choices, and cost reduction pressures continue over a product's lifetime.
Table 1 lists advantages for flip-chip and wire bonding. Many of the advantages depend on the specific application details.
Often, both processes offer advantages. An example is cost. The total cost for a wire-bonded package in the <600-I/O range is typically much less than for an equivalent flip-chip package. But for a high-volume application, with chips designed and die size minimized to take advantage of flip-chip's efficient use of silicon real estate, wafer cost reductions can significantly lower the total cost per flip-chip package below that of the comparable wire bonded package. Advantages In general, the flexibility, infrastructure and cost of wire bonding are its major advantages. Package size is smaller, and device speed is normally higher for flip-chip. System speeds with wire-bonded packages designed for high signal-propagation rates (e.g., RDRAM, BOC), however, remain competitive4. Flip-chip devices often have many more bumps than equivalent wire-bonded devices have bond pads. Because the bumping cost/wafer is fixed (independent of how many bumps there are per wafer), there are electrical advantages to designing in additional bumps. As chip voltages drop and current requirements increase, it is advantageous to distribute power and ground directly to the core of the devices, with area array solder bumps to minimize voltage drop. These low-inductance power and ground paths also minimize SSN (simultaneous switching noise) and ground bounce. On especially sensitive signal paths, additional power and ground bumps can be used to surround the sensitive I/O bump, shielding the bump from noise induced by neighboring circuitry. Process Descriptions Table 2 shows process flow for both flip-chip and wire bonding on an organic substrate.
For flip-chip wafers that were originally designed with peripheral pad layouts for wire bonding, more steps are added. The wafer-bumping stage includes redistribution of the peripheral bond pads to an area array design. Dielectric and metal layers are added to redistribute and connect the aluminum bond pads to area array bumps. The Differences The two processes are substantially different from an automation perspective. Wire bonding is best characterized as a single-point-unit operation. Each bond is individually produced. Die on their carrier or substrate are moved through a wire bonder. The machine's pattern recognition system identifies the die, transforms and corrects the taught locations for each bond, and individually moves to each location to produce an interconnection. Flip-chip is a wafer-scale operation. Bumps are formed on an entire wafer, and the wafer is diced; individual die are picked, fluxed and placed on the substrate. The flux must be tacky enough to hold the die in place for handling through reflow. The solder is reflowed above its melting point to form the interconnection. Underfill and encapsulation processes complete the assembly. At all times, the process handles entire wafers, die or substrates. It is never a single-point operation. Ultra-CSP WLPs, such as the Flip Chip Technologies' Ultra-CSP shown in Figure 2, are CSPs that are processed at the wafer level. The WLP opens up new CSP applications in both low-I/O-count packages and those that require very small form factors. In most applications, the Ultra-CSP does not require underfill, providing additional opportunities for cost reduction.
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