TECHNICAL BENEFITS Technology Thresholds Current leading-edge flip-chip designs are in production with as many as 5,908 bumps/chip at 200-µm pitch and 1,500 bumps/chip at 170-µm pitch in area array configurations. Figure 3 shows a high I/O-flip-chip device at 178-µm pitch full area array. Future production area array pitches will continue to reduce to 150-µm in the next two years and eventually to the 100-125-µm range as the substrate technology becomes cost effective. The rate of pitch reduction is likely to moderate as design tools become available to take full advantage of the area array capabilities of flip-chip technology.
Current mass production for wire bonding is in the 60-µm range, and a production capability of 50-µm is believed to represent the leading edge in wire bonding.
Getting the Lead Out An inherent advantage of thermosonic/ ultrasonic bonding is that there is a true weld, joining the two metals through an inter-metallic phase. Conversely, all flip-chip devices use solder interconnects, formulated in two, three- and four-part (binary, ternary and quaternary) alloys. Solder is a metallic alloy with a low melting point. The solder melts (reflows) and the liquid phase wets the two metals that are joined. When the solder solidifies, it provides a mechanically strong joint with low electrical resistance. The best solder alloys for flip-chip applications are the Sn/Ag/Cu alloy systems, with the possible inclusion of an additional element. A solder bumping technology, such as solder paste, is preferred over plating to achieve the control of the elements in the alloy as bumped. Typical electrical solders contain lead-this is expected to change as lead-free alloys are introduced. Lead-free telecommunications devices will be on the market this year. Green marketing is the primary driver for the development and commercialization of lead-free solder technology. Once the first device marketed and advertised with lead-free logos and designated as environmentally friendly enters the marketplace, it will be a primary qualifier for an OEM in doing business. Ternary and quaternary lead-free solder alloys will be the primary choices for these products. An additional benefit of lead-free alloy systems is that they have the potential to minimize the soft errors produced by lead alloys. These errors are caused by alpha particle emissions from radioactive isotopes common in Pb-based alloys. In Japan, many OEMs will specify lead-free to meet upcoming legal requirements. In Europe and the U.S., the telecom market will demand this feature as a basis for conducting business. Reliability Flip-chip processes include fluxing, placement and reflow, as well as the underfill material and dispensing processes. Under-fill is normally required for flip-chip devices on laminate substrates to eliminate solder fatigue. This fatigue is caused by cyclic strain resulting from a TCE mismatch between the chip and the substrate during thermal cycling. The underfill must be stiff enough to restrain the large expansion/ contraction of the laminate and reduce the strain on the solder bump. A well-characterized flip-chip assembly process can achieve high yields and reliability. Fine-pitch wire bonding is also a complicated process. Molding fine-pitch wire bonds requires additional process capabilities to avoid wire sweep and deflection. Finer diameter wires, required to achieve fine pitch, are not as strong or as stiff as larger diameter wires. To address these constraints, manufacturers are developing higher strength wire alloys, copper-wire bonding and encapsulant formulations to minimize sweep at fine pitches and with long wires. Through process integration, additional supplier support, and improved equipment and materials capabilities, fine-pitch wire bonding also can achieve high yields and reliability. Cost Analysis Cost comparisons and analyses are highly dependent on modeling conditions and, in particular, are sensitive to the choice of substrate technology. Optimum substrate choices often change through the life of a product, depend/ing on production volume, substrate layers, microvias5 vs. conventional multilayer, among other considerations.
Technical reasons requiring flip-chip's electrical performance or form factor are usually the most important criteria for a change from wire bonding to flip chip. Wafers designed specifically for area array flip-chip may have smaller die, because peripheral bond-pad layout (in pad-limited devices) requires a larger die perimeter to escape the required I/O. Die size is a dominant factor in the cost of a chip and represents a significant advantage for flip-chip. This advantage, however, may be reduced, because the additional substrate density, required to escape the area array flip-chip bumps, may be more costly and require additional substrate layers or microvia technology. High-Speed Packages Three years ago the SIA roadmap6 and other sources predicted that the speed required for new devices would soon exceed the capabilities of wire bonding and that flip-chip would be the interconnection method able to meet the speed requirements of advanced packaging. Today, the same prediction can be made, but the edge of the envelope has been redefined. RAMBUS' RDRAM and board-on-chip packaging is being produced with wire-bonded interconnections operating at speeds of 400 MHz, which were not considered feasible only a few years ago. Wire-bonded RF packages with speeds of 2.4 GHz are available today. Future packaging designs, with short wire lengths and very fine bond pitch, will continue to push out the edge of the envelope for the foreseeable future. Flip-chip still has a technology advantage, but wire bonding remains highly competitive. The Future Both wire bonding and flip-chip will continue to coexist as growth technologies into the foreseeable future, and the IC packaging market will remain a continuum of technology choices. Where flip-chip is advantageous, it will be the production method. As the flip-chip infrastructure is established, costs will be reduced and the application space will broaden. Where applications can be produced by wire bonding, its cost advantages will determine the interconnect method. New technologies, such as WLP, WLBI (wafer-level burn-in), stacked packages and optical interconnects, as well as incremental advances in current technologies-such as flip-chip and wire bonding-will continue to redefine the continuum of product and process solutions for the interconnection of the die to the external world. References
|
