Common Needs LSI Logic led the way through the 90s in creating the organic substrate merchant supply base for flip-chip-in-package, Dr. Nakahara adds, but Altera, IBM, Intel, Xilinx and others were not far behind because they were driven by common needs. (IBM was working with organic substrates in the lab in the early 1990s.) LSI Logic is a Silicon Valley-based, oldline producer of large, complex ASICs (running head-to-head with IBM's Microelectronics Division in sales). LSI's package development group devised standard substrate platforms to accommodate the spectrum of chip sizes, offering differential pair leads with metal core grounding. The company was an early user of PTFE microvia substrates fabricated by a W.L. Gore division, (since acquired by 3M) in Eau Claire, Wis., Amkor, ASE and ChipPAC have licensed LSI's organic laminate package technology-any or all are supply partners for production requirements. Ed Fulcher, who heads up LSI Logic's package development group, says that both solder paste and electroplated metallization for bump formation meet his needs. Moving Up PLDs and microprocessors are also moving up in leadcount and performance, requiring flip-chip packages. Altera has placed TMSC, its wafer foundry, in the bumping business for organic substrates. Intel, too, has opted for flip-chip on organic substrates. The Land Grid Array-packaged Pentium 4 has 1800 flip-chip bumps for 495 lands. (The bump count came from a private source.) In 2000, Intel may have electroplated bumps for more than 60 million flip-chip IC packages. IBM Endicott, which is busy making organic substrates, sells them in packages for itself and others. IBM Microelectronics electroplates solder on wafers whose dice are flip-chipped on build-up organic substrates fabricated in Endicott and assembled as packages in Bromont. One example, introduced in 2000, is the HyperBGA which uses PTFE.5 In October 2000, IBM Microelectronics announced a $5 billion expansion that includes organic substrate packaging. Substrate Perspectives All the substrates in all the packages mentioned, and others, offer bump pitches that exceed 200 µm. Resolution to 50 µm is doable, but today's substrate art doesn't permit enough circuit escape from denser arrayed contacts. According to the 1999 International Technology Roadmap for Semiconductors, 150 µm flip-chip pitch will be needed to accommodate the I/O counts and densities of 2005. The build-up substrates of today with 35 µm lines/spaces and 50 µm vias still aren't good enough. The challenge is to develop new substrate technologies, capable of closing the packaging gap. Two approaches promise to do it. One is offered by the Kulicke & Soffa Substrate Division (formerly X-Lam) in San Jose.6 The thinfilm UltraVIA process reduces dimensions by about 50%, allowing flip-chip pitch to decrease to150 µm. The K&S vision is to reinvent itself. As the key factor in the dominant wire- bonding technology for connecting chips, the company had a window on a future that will belong to flip-chips, not wirebonds. It recently acquired Delphi Delco's interest in what was formerly known as Flip Chip Technologies (now K&S' Flip Chip Division). At Alpine Microsystems, a high-density silicon substrate approach achieves 125 µm flip-chip pitch. Alpine employs microelectronics fabrication to achieve 25 µm lines and vias on the substrate. However, the company's model at this time is to provide complete modules, not substrates. But things can change. The Technology Enablers The 1990s were a pivotal decade for the flip-chip market and technology development. Metallization and substrate advances were major contributors. Other enabling factors were advances in UBM, redistribution, underfills, new test approaches, new lithography tools and process equipment, such as wafer thinning and low-alpha solder. IBM introduced underfill2 in 1990. It made organic substrates reliable by moderating the difference between the CTE of silicon and organic substrates. A great effort has gone into underfill development; a recent one is notable. Cookson Plaskon, followed by Loctite Dexter, offered molding compounds in the late '90s for device encapsulation that also underfill in one operation. Other underfill suppliers are Emerson & Cumming and there will be a rejuvenated Honeywell Electronic Materials, as part of GE Specialty Materials. GE likes complementary high-growth niche markets related to its main businesses. Redistribution of pads from peripheral to arrayed locations, build-up technology, and photosensitive resist masking for bump pad processing have all been greatly facilitated by Dow's BCB. The Dow formula offers easy application, curing, good planarity and low moisture absorption. BCB became available in 1990, another flip-chip enabler in the '90s. Bump lithography tools gained new sophistication when Ultratech discovered the backend. Steppers speed throughput, process any film and cover a wide spectral range. Bumps are physically close to the chip. To avoid memory and logic soft errors, low alpha lead, with less than 0.1 alpha count/hour/cm sq., is needed. Cookson, Mitsubishi and Honeywell Electronic Materials (part of GE Specialty Materials by the time you read this), are sources.
Larger, Thicker Wafers As wafers become larger, they also become thicker. Larger wafers are also aimed at larger chips. This combination promotes rigidity and contributes to temperature cycling stress. Thinning wafers after metallization is desirable, since they need to be rugged to be handled through that process. Companies such as Tru-Si Technologies, San Jose, offer equipment for stress-free plasma thinning. Wafer-Level Packaging Batch packaging7 at the wafer level before singulation provides such enormous economies of scale that integrated device manufacturers (IDMs), in applicable IC product families, feel compelled to participate. Assembly on board using chip shooters makes the total manufacturing economics even more attractive and threatens chip-on-board. We've listed most of the independents who offer wafer bumping/flip-chip packaging below. There will be some omissions, likely because some companies failed to return our survey by the deadline. Independents with proprietary WLPs include Amkor, Fujitsu and Mitsubishi. We might also mention the licensing companies that offer proprietary wafer-level packages. With the exception of ShellCase, which is based in Israel, they're all in Silicon Valley, and include FormFactor, MicroSMD and Tessera. A Challenge to Flip-Chip
A few of these represent the most successful challenge so far to flip-chip. For example, Tessera's flexible interconnect with elastomer base (Figure 5) is used by Intel. FormFactor's MicroSpring contact (Figure 6) offers superior test economics. Both companies have amassed significant licensee portfolios. Many of the approaches may use discrete solder balls at die level instead of reflowed bumps. Several cost and performance tradeoffs determine the choice. New wafer-level packaging foundries seem to be emerging almost daily. Some with substantial technology and experience behind them include Advanced Interconnect Solutions (Figure 7), headed by IPAC founder Victor Batinovich and Japan's IEP. The latter has its roots in Oki and Casio and is headed by Henry Kobayashi. Unit potential for DRAM, SRAM, Flash and ROM is over 9 billion/year. For Analog the unit potential is over 22 billion/ year8, using 1999 annual shipments. Most interconnections are FC, but other technologies are contending for this enormous market. Wafer-Bumping Services Our table lists more than 15 entries, companies. The list will never be inclusive because it seems as though new flip-chip bumping service companies are springing up as we speak. We used a rather loose definition of "bumping services," so we included intermediaries and package companies in some cases. Since there isn't space to profile every company, we'll make note of some interesting features of the group and some of its members. There is a trend to locate near foundries for better logistics. That is why so many are springing up in Taiwan-close to TMSC and UMC or locating in Singapore-close to Chartered, etc. The Leaders Amkor is establishing a bumping facility in Korea with both paste deposition and plating metallization. The technology is licensed from K&S and Unitive. The two leading services are the K&S Flip Chip Division in Phoenix, Ariz. and Unitive Electronics Inc., Research Triangle Park, N.C., with an affiliate in Taiwan. These companies compete on several fronts: a) K&S deposits solder paste while Unitive plates; b) each has a wafer level package, so each aims at both high lead count ICs and mass memory markets. Their visions are quite different. K&S licenses its technology widely; Unitive is more selective and more limited in its licensing. Another likely competitor to K&S and Unitive is PacTech, which is now offering bumping in Europe. Soon, Pac Tech will open an electroless bumping facility in Silicon Valley. While some offshore companies will bring their bumping lines to Silicon Valley, Silicon Glen or the Silicon Desert, others believe the future belongs offshore. Focus Interconnect has left Austin, Texas and is expanding in Singapore, with an electroplating bump service. Picopak electroless operations have left Finland and are now offering bumping services in Malaysia.
Conclusion Certainly the flip-chip of 32 years ago and the flip-chip of today bear substantive differences. Yet, the geneology is quite similar. Once the flip-chip bandwagon began to roll, there was no stopping it. Certainly the enabling technologies that allow for a low-cost bumping process have ensured flip-chip's very bright future through the next decade and beyond. References 1. R. Tummala and E.J Rymaszewski, Microelectronics Packaging Handbook, 1989, pp 367-373. 2. K. Gilleo, Tutorial 6, flipchips.com, 2001. 3. G. Riley, flipchips.com, 2001. 4. Tummala, p. 369. 5. Gilleo. 6. J. Strandberg on Substrates, Connections, K&S Volume 1, 2000. 7. Tom Chung, Wafer Level Packaging, Etronix, 2001. 8. InfraFOCUS custom market study, Palo Alto, Calif., 1999.
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