By Jerry Secrest, Secrest Research, San Jose Discussing the topic of Known-Good Die is a little like going to Aunt Marian's for Thanksgiving dinner. You like Aunt Marian, but you're afraid-for some reason-to get near her! For its diminutive size, KGD has earned more than its share of controversy over the years-mostly because for so long it was so difficult to obtain KGD from the companies that could supply it. Why is the topic of KGD important? Because there is a strong market for semiconductor products in stacked CSPs. The Cell Phone Market One of these major KGD markets is cell phones, and one forecaster estimates that 500 million cell phones will be sold this year. Most of these phones will contain a stacked CSP containing a flash RAM and a static RAM. Additionally, there are strong markets for other handheld electronic products, such as electronic calendar-phone books. The majority of consumer products need semiconductors that occupy a small area, possess low weight and, most of all, offer high performance. Integrated circuits in S-CSPs fit these needs. KGD assists S-CSP manufacturing by enabling high S-CSP test yields and reliability. What's a KGD? According to the Die Products Consortium (DPC)*, "KGD is a process that provides the same levels of certainty . . . that the die product meets the equivalent quality and reliability targets as packaged parts." An important word in this definition is "process." It is important because achieving high quality and reliability in a die product requires a manufacturing process and sequence that changes to meet the objective. For example, the process to make a KGD for a toy can be quite different from the process employed to make a KGD for an airplane guidance system. The author's own definition for KGD is, A die-form semiconductor product that meets or exceeds the product specifications, quality, and reliability required by the application.
Manufacturing Figure 1 is a typical manufacturing flow for making KGD. Wafer fab and E-test are included in the flow because they can play a significant role in achieving working KGD. While the flow shown appears to be simple, there are many variations to it. For example, it may not require interconnect redistribution if bumps are placed over bonding pads. Also, if the wafer is thinned slightly (or not at all), mounting for the saw may be done after KGD testing. S-CSPs need thin die to allow 2-3 to fit into a package form-factor of 1.4 mm high. This means that KGD for S-CSPs will have to be tested in a sawn wafer form in a frame after thinning. (There are many more variations in KGD manufacturing. We will look at a few associated with test later in this article.)
KGD Testing Is there a single test method for KGD? Probably not. There are too many product/process options and applications. (Figure 2 shows some of the factors that can affect KGD test.) The figure shows only broad factors. For example, underneath the "Memory" item, there are several options such as DRAM, SRAM or flash. Die testing varies widely, based on the product. Memory products are commonly tested in parallel to reduce cost, and because there are relatively few I/O pins for the amount of memory. The low I/O and high volume makes it practical and economical to set up KGD for parallel testing. Logic has a relatively large number of pins per die and a lower production volume per design. This makes it technically more difficult and less economical to parallel test. Analog Products Special thought needs to be given to some analog products shipped in a die format, because they may contain ultralow-current circuits that require matching. These circuits have been known to shift during the assembly process, which changes the product characteristics and may even result in the circuit falling out of spec. While this situation is not the fault of the testing, thought needs to go into the testing and handling to minimize any potential for shift. The selected application can change the test criteria for KGD. For example, some OEM products may have a lifetime of one year and may be used for less than 1,000 hours. For this application, the testing needs to ensure that there is a minimum failure-in-time (FIT), in the early application life. Another application may be in a transceiver that needs to work for five years. In this case, the long-term FIT needs to be at a minimum. Test Content There are different test methods needed across applications, products and processes. The objective of all methods, however, is to supply die products that meet product specifications over the defined temperature range for:
Function Tests There are typically two stages for function tests: gross and fault coverage. Gross function failures are picked up by the tests for power supply opens and shorts, input/output opens and shorts, and Iddq. The function test and fault coverage tests place signals-test vectors on the input pins-and checks for the correct signals on output pins. The first few function tests pick up a high percentage of the remaining defective die. As the number of input vectors increases, defective die are detected on a declining basis. The results of the decline: It takes many more test vectors to pick up fewer function faults. Speed tests have typically been performed after packaging. Now, with the requirement for KGD, these tests needs to be done in wafer form. At-speed testing is more difficult during wafer test because there is a longer probe length for the signals to travel. In addition, for CMOS circuits, the IC speed decreases with increasing temperature. This can mean that wafer test for KGD needs to be done at elevated temperatures. An alternative to speed testing is to predict product speed from fab and E-test data. Reliability If the product or application requires burn-in to improve the reliability of the KGD, there are two basic techniques for supplying it: 1. Burn in the die while they are still together on the wafer; 2. Burn in the singulated die. Wafer Burn-In There are two similar techniques for wafer burn-in. One technique employs sacrificial interconnect layers on the wafer to supply power and signal to the die. The sacrificial layers are put on the wafers in a manner similar to fab processing. After processing, the wafer is loaded into a fixture supplying power, signal and temperature control during the burn-in cycle. The interconnect layer is stripped after the burn-in and the die on the wafer are tested. A second technique uses an interconnect layer on a film, with the wafer and film aligned and placed in the fixture. Die can be burned-in, which may require custom sockets. Obviously, loading and unloading die from carriers to burn-in sockets without inducing damage is required. Another approach to improving reliability is to remove die at KGD test that have a higher probability of failing during use. Some techniques for removing weaker die are:
Die Identification Packaged parts can be traced back to final test via the date code and other data on the package. Die product ICs also have to be identified, for which there are three common approaches:
The Beginning It is typical to close a discussion with a conclusion or summary. However, in this case, we are just at the opening phases of KGD. There is current need for KGD in stacked CSP, and market signals point to higher volumes of KGD being used in the future. A couple of these uses are Palm-type products combined with cell phones and cache memory in the same package with microprocessors. There are multiple manufacturing paths to making KGD to meet end product and application needs. The DPC is an organization of suppliers to and vendors of KGD. It sponsors quarterly meetings and a yearly September KGD workshop in Napa, Calif. Contact DPC through its website at www.dieproduct.com.
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