By Dr. Puligandla Viswanadham, Nokia Mobile Phones Inc., Irving, Texas
One of today's most pervasive, versatile and portable modern electronic appliances is the mobile phone. The market penetration of mobile communications hardware is phenomenal and is increasing at an exponential rate. This is in stark contrast to the PC and notebook industries, where the growth is slow and linear. In addition to being mobile, cellular phones have indeed become personal and personalized. They can also be called wearable or "intangible personal assistants," as they become the most pervasive and prominent communications platform. In this role, they also constitute the largest customer base for information management. Expanding Applications The applications for mobile phones are ever expanding: voice mail, text messaging, e-mail, Internet browsing, maps, travel reservations, directories, stock quotes, software updates, news, global positioning systems, etc.(1) Important elements in modern portable electronic products are versatility, portability, lowest cost per function, speed-to-market, high reliability and-even more importantly-visual and ergonomic appeal. These elements constitute laudable goals that require aggressive innovation in packaging. The environment is one of increasing consumer demand for lighter and cheaper mobile communication products with superior functionality. In the next five or so years, cellular phones may undergo a weight and volume reduction by as much as 20 percent annually. The printed wiring board technology is likely to experience wiring board density increases (through reduction of line width/spaces) to 50 µm, micro-via diameters of 50 µm, one to three layers of surface redistribution layers and board thicknesses down to almost 0.5 mm. Second-level package miniaturization will be driven to better than what is attainable by single device flip-chip attach through the adoption of such concepts as chip stacking and System-in-Package (SiP). Hardware miniaturization and integration needs to occur at all levels of packaging. In fact, a drive towards elimination of some levels of packaging is imperative. Conceptually, a high level of function integration at lowest cost is possible through silicon integration. Single-chip integration of total radio frequency requirements such as high Q, band pass filters, antenna switches, etc., may be well-near impossible at the present time, due to coupling between various functional segments that can impact signal-to-noise ratios. One may encounter performance as well as yield issues in such scenarios. Thus, package-shrinking efforts are gaining more attention as near-term solutions. CSPs, high-density laminates and highly automated assembly processes are emerging and maturing to meet industry demands.
Package Miniaturization The thin Small Outline Package (TSOP) came into existence in the late '80s to meet the form-factor requirements of the Personal Computer Memory Card Industry Association (PCMCIA) standards. Another advance, personified by the ball grid array (BGA) package, evolved to alleviate the assembly problems associated with high-pin-count, fine-pitch, gull-wing leaded quad flat packs. The low-standoff TSOPs with stiff Alloy-42 leads have created thermal cycling reliability concerns, which prompted miniaturization of area array packages leading to chip-size packages. There are now more than a hundred varieties of CSPs with different interposer designs, materials and lead forms. (CSPs became mainstream packages for cellular phones around 1997.) Further miniaturization is needed to meet the ever-growing demand for functionality with portability. In some packaging concepts, chips are bonded in a parallel-as opposed to stacked-fashion on organic laminates such as BT resin. A 128 Mb synchronized DRAM packaged in 54-leaded Type II TSOP has been reported. A package thermal cycling reliability of 300 cycles in the -65 to 150°C range was indicated(2), and no board level reliability problems were reported. Typical reliability exposures in this type of package are voids due to the adhesive tape, associated moisture entrapment and delamination during reflow operations. 3D Packaging Conceptually, chip-scale packaging and flip-chip attach set a limit on maximal area density on the PWB. Increased functionality and performance in minimal space, weight and volume is envisaged through exploration of such concepts as system-on-a-chip (SOC) and SiP. As a result, 3D packaging using z-axis stacking concept is being investigated for increasing packaging density(3). Two approaches are prevalent for resin-encapsulated packages, namely, package stacking itself or chip stacking inside the package(4-8). Vertical stacking of packages, as a means of increasing area density of the circuit card assembly, began almost five years ago. Two- and three-high stack packages in J-lead, gullwing, and bottom-leaded formats have been reported in the literature(9).
Figure 1 shows an example of two- and four-high stacked, bottom-leaded packages. Stacked-chip packages in leaded TSOP II format with good thermal performance have been reported for a 128 Mb SDRAM application. The leadframes of individual devices are soldered together, as shown. In this case, the leadframes themselves serve as interposers between the adjacent silicon devices and the package is overmolded(8). The emergence of chip-size packages with flexible interposers facilitated the development of stacked flash memory and static random access memory chip-size packages. The alternative approach is to stack the individual silicon devices and interconnect the devices and the substrate together either by (C4), wirebonding or a combination thereof. Area and Weight Reduction A 60 percent reduction in area and weight are possible by migrating from two separate TSOPs to a stacked CSP. Recently, the development of triple-chip-stacked packages termed "Stacked System Integra-tion Packages" was reported. In this type of package combination, flash and SRAM-or ASIC, flash and SRAM-are stacked together on polyimide substrates with wirebonding as the interconnect medium. The terminations on the underside of the chip carrier are 0.8 mm-pitch area array solder ball interconnects. The maximum package height was maintained at 1.4 mm by backlapping the chips to a thickness of 150 µm to meet the JEDEC standard. The mounting surface area and the package weight of the stacked device are smaller than that for the so-called bare die attach, and the package is also provided with vent holes on the underside to minimize moisture-related concerns during the board level assembly(10-11). Board level thermal cycling reliability in excess of 7-800 cycles in the -40 to 125°C range was indicated. Chip stacking may be cheaper than package stacking. Chip-stack package reliability is expected to be comparable to TSOP reliability, while package stack could be inferior to TSOPs, due to the additional solder joints involved between packages. However, thermal cycling reliability of 200 cycles in the range of -65 to 150°C, and 168 hours of pressure cooker test at 121°C and 100 percent r.h. were demonstrated for a 128 Mb SDRAM stacked-chip package (SCP) with a leadframe interposer(12), which is comparable to a TSOP package. Technical Challenges Several technical challenges are imperative in chip-stacking technology. These include:
In addition, the package has to meet the JEDEC standards. In flip-chip attach, one also has to deal with the requirements for the PWB technology, underfilling, flip-chip rework, the second-level assembly and the reliability aspects. Laminate/Carrier High-density devices require high-density substrates and PWB materials. This has not been a problem with ceramic substrates; however, it has been a challenge with organic laminates. A convergence of chip carrier and PWB technologies to accommodate high-density devices is taking place. A number of high-density laminates capable of 75 µm line space and widths and 125 µm vias have emerged in recent years. These laminates include surface laminar circuitry (SLC), any layer inner via hole (ALIVH), and others that utilize either photo-imageable or laser-drilled vias. The limitations of conventional PWB fabrication processes are being overcome, and a laser structuring technique capable of 50 µm line widths and spaces and 70 µm diameter vias has been reported recently(13). Users, however, should recognize that the capabilities very much depend on the nature of the organic dielectric being lased, or the thickness of the copper being circuitized. Laser structuring has been demonstrated for both conventional organic laminate as well as injection-molded liquid crystal polymers. As one migrates to finer-pitch chip-scale packages, such as 0.5 mm or finer, aspects of printed wiring board surface finish may play a larger role in the reliability of the assemblies. A two- to five-micro-inch layer of immersion gold over a 150- micro-inch layer of electroless nickel is a common finish. At these thicknesses, the gold tends to be porous, and the oxidation of underlying nickel poses a solderability concern. If the thickness of gold is increased to reduce porosity, the amount of gold may exceed the gold content limit in the solder joint, and embrittlement may constitute a reliability exposure. 'Black Pad' Problem Another solderability-and hence reliability-exposure that has appeared in recent years is the so-called "black pad" problem. This has been attributed to the hyper-corrosivity of the gold plating bath that increases the phosphorous content of the nickel layer and also renders the nickel layer less solderable(14-15). Black pad can lead to poor solder joints during the assembly process, and eventually it may pose a reliability risk under both mechanical and thermal stresses. Alternative surface finishes such as immersion silver, nickel-palladium and immersion tin are slowly emerging, and it is important to gain an understanding of the nature and behavior of these surfaces16-17. Optimized thermal and electrical performance is key for the utilization of these technologies. Finer lithographic techniques are essential for the organic chip carrier fabrication as well as the PWB. SOC Versus SiP Migration from individual component and packaging technology concepts to SOC or a SiP concept is essential to reaching the levels of miniaturization envisaged for mobile communication hardware such as cellular phones. One authority calls for a 14 percent annual reduction on PWB area and a 15 percent annual reduction in weight(11). The sixty-gram weight in 60 cubic centimeter space benchmark is probably attainable with such concepts as 3D stacked chips or packages. However, further miniaturization may require additional, innovative packaging concepts.
Lack of Co-Design Certain items, such as a lack of co-design and test methodologies, model libraries for modeling and design and limitations in the ability to integrate heterogeneous components and technologies, may make system-on-a-chip more difficult to realize than originally conceived.
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