Current Issue An Independent Journal Dedicated to the Advancement of Chip - Scale Electronics July 2001 Email the editor

Dr. Tadatomo Suga Dr. Tadatomo Suga, a professor at the University of Tokyo's Research Center for Advanced Science and Technology (RCAST), is one of the world's pre-eminent experts on IC interconnection and packaging. His responsibilities at the Center include both the Microsystem Integration and Packaging Laboratory (MSIP) and Nanometer-scale Manufacturing Science Laboratory (NMS). Dr. Suga earned a doctorate in materials science from Stuttgart University (Germany) in 1983. Chip Scale Review interviewed Dr. Suga at Stanford University, Palo Alto, Calif., which he was at the University's U.S.-Japan Technology Management Center for the spring lecture series on "The Impact of Wafer-Level Technologies on Advanced IC Design." He is the author of "Room-Temperature Bonding (Surface-Activated Bonding) and its Applications in Microelectronics" presented during the Stanford series. [fuji.stanford.edu/seminars/spring01]

Q What is the concept behind surface-activated bonding (SAB)?

A It is a method for joining dissimilar materials at room temperature. Developed over the past 10 years, it is based on the reactivity of atomically clean surfaces of solids and the formation of chemical bonds in contact between the clean and activated surfaces.

The bonding consists of cleaning the surfaces by ion or radical beam irradiation and contact in an ultrahigh vacuum or in an inert gas, depending on the materials combination and the characteristics required by the bonding. In 1998, 24 Japanese companies founded the Institute of Advanced Microsystems Integration (IMSI) to promote SAB in collaboration with the University of Tokyo. This is the first time that Japanese competitors in the electronic packaging field have worked together.

Q What companies are involved in the IMSI?

A The consortium consists of Fujitsu Ltd., Hitachi, Matsushita Electronic Co., Mitsubishi Electric Co., NEC, Oki Electric Industry Co., ROHM, Sanyo Electric, Sharp, Sony and Toshiba. They are "Industry Alliance Members" who each pay $50,000 a year for membership. There are also more than a dozen "Industry Liaison Members," who are mostly materials suppliers.

Q What does the SAB process involve?

A The key items are the surface-activating process and the alignment and manipulation of the chip. So far, several surface-activated pieces of equipment have been developed, including a cold-rolling machine for manufacturing metal laminates and a bonding machine for wafers up to 200 mm. Collaborating with Toray Engineering, we have modified a commercial flip-chip bonder and equipped it with an additional chamber for the pre-treatment of the substrates (see figure).

Modified flip-chip bonder developed by the University of Tokyo and TORAY Engineering

Q What advantages does SAB offer?

A SAB represents a new type of interconnection technology that reaches into the area of design rules and on-chip interconnects. Today, there is a technologies gap between wiring for packaging and wiring on chip. It is likely that 25-micron features will be the limit for current flip-chip technologies. Pitches smaller than 25 microns will require new methods and new machines. SAB is also performed at room temperature versus the higher temperatures of traditional bonding methods. Al-Al laminates fabricated by SAB have been put into practical applications for a part of the safety vent for the Li-ion battery. Currently almost 10 million pieces of this vent are produced each month.

The on-chip delay in signal transmission is also a major issue in designing and fabricating LSI chips. SAB is bumpless and can bond wiring layers to wafers at a several micron pad size, a very tight pitch less than 10 microns. Instead of bumps, there are "pins"-more than one million-(contacts) that stick out a bit. This method of joining offers the advantages of intra-chip wiring, where the contacts essentially cause zero delay. This bumpless interconnect represents a type of flip-chip bonding, initially done with silicon to silicon.

Q What are the key applications?

A There are a number of viable applications, including the ultrafine-pitch interconnections for electronic packaging, wafer-direct bonding for hetero-junction semiconductors and MEMs, especially those that include sensors. SAB can be employed for any material that is now packaged by flip-chip bonding.

It is also particularly well-suited to packaging fragile ICs, such as those created from gallium arsenide and indium phosphide, because the joining forces (reduced by the SAB cleaning process) are much lower than those employed in wire bonding. While the bumpless technology is at least five years from production use, the same methods can be used for micron-pitch bumping.

Q What are the environmental aspects of SAB?

A SAB addresses the challenges to establish a method for "smart" disassembly of electronic products by using reverse engineering. The reversible interconnection based on room-temperature bonding will provide one of the methods for smart disassembly. Other environmental concerns address EcoDesign and the use of lead-free solders.

Q Is the level of packaging in Japan more advanced than the U.S.?

A That's difficult to say. Production engineering at Japanese companies is quite advanced, but the development of new technology is comparable to the U.S. It's possible that the U.S. has more potential in new packaging technologies due to its background in high-end packaging for aerospace applications.

Q To move to another topic, are Japanese companies interested in transferring their advanced packaging technology outside the country, to China for example?

A Many Japanese companies are building manufacturing sites in China, and China is an important location for packaging. Some packaging technology will certainly go into China. Many Japanese companies, however, will not transfer their advanced CSP development outside the country. This desire to retain it inside Japan is no different from what Intel or Tessera has done.