Current Issue An Independent Journal Dedicated to the Advancement of Chip - Scale Electronics July 2001 Email the editor

Amkor Offering Exposed Pad LQFP Format

Chandler, Ariz.-Amkor Technologies Inc. has expanded its family of low-profile QFC packages to include an exposed pad configuration in 20x20, 24 x 24 and 28 x 28 mm form factors.

Amkor claims its proprietary ExposedPad LQFP provides up to 60 percent better power and enhanced thermal performance for cost-effective applications requiring high speed, low loop inductance and a short path to ground in a low-profile package. Typical uses include laptops, disk drives, A/V devices and data acquisition devices. [amkor.com]

ASAT Installs Lead-Free Hong Kong Line

Hong Kong-ASAT has installed a dedicated lead-free plating line at the company's Hong Kong facility.

The company says that it now offers lead-free solder with tin, silver and copper alloy (SnAgCu) leaded products containing pure matte tin (Sn) and its proprietary gold plated TAPP IC packages. [asat.com]

Chip Supply Named Microchip Die Partner

Orlando, Fla.-Chip Supply Inc. has been named the first distribution partner that will specialize in die and wafer form for Microchip Technology's PICmicro microcontrollers, stand-alone analog devices and all other products. [chipsupply.com]

NSEB Relocates Sunnyvale, Calif. Office

Sunnyvale, Calif.-NSE (USA), the U.S.-based sales and marketing group for NS Electronics Bangkok (NSEB) has relocated to 298 S. Sunnyvale Ave., DeAnza Building, Suite 201, Sunnyvale, CA 94086. The phone and fax numbers are unchanged. [nseb.com]

Walsin's recently patented leadframe structure

Walsin, Taiwan, Granted Patent for a Leadframe

Washington-Walsin Advanced Electronics Ltd., Kaohsiung, Taiwan, has been granted U.S. Patent #6,204,553 for a leadframe structure.

The leadframe includes a die pad and many leads. One surface of the die pad supports a Si chip while the other surface has many annular grooves, all with the same geometric center.

The inner lead portion of the leads surrounds the die pad, but the pad and the leads are on different planar surfaces.

The inventors were Wen-Chun Liu, Hui-Ping Liu, Jung-Jie Liou, Yi-Hsiang Pan and Sheng-Tung Tsai. [wae.com]

Kingpak Technology Introduces New Wire Bonded Stacked CSP

Taipei, Taiwan-Kingpak Technology has introduced a low-cost, high-reliability production process for doubling the density of semiconductor memory within a single chip-scale BGA package.

SEM illustrates wire sweep in Kingpak's Stacked BGA.

The technique is derived from the stacked CSP method for building multi-chip combination devices, but stacks two of the same (or similar-sized) die in the same BGA package.

Applications include cell phones and other portable devices that require greater memory capacity in smaller spaces, as well as super-high-density modules.

By employing special techniques to attain wire loop heights of less than 2 mils, same die size stacking can be achieved with conventional wirebonding, so existing memory ICs can be used.

Since memory devices can be connected together, sharing many of the same signal lines, BGA substrate designs are generally no more complex than those used for single memory chip assembly, according to Kingpak's Martin Paul.

Even with a low-cost PWB substrate, a stacked BGA package can be built to an overall package height of 1.2-1.4 mm.

Die from both devices are thinned in wafer form to an 8 mil thickness, allowing the stacked assembly, including both the die bond lines and wire loop heights, to be contained in a 0.7 mm mold-chase height.

Thin substrates fabricated from 0.21 mm BT material are used, so the entire package thickness is dependent only on the solder-ball diameter. [kingpak.com]

A new European Test Development Center will join STATS' Singapore facilities (shown) to broaden the company's international reach.

STATS Opens European Test Development Center

Singapore-ST Assembly Test Services Ltd. (STATS) has opened a new Test Development Center in Surrey, U.K.

The new facility is part of STATS' strategy to expand worldwide engineering support for customers. Together with two test development centers, located in Singapore and the U.S., STATS says this helps the company form a global network for dedicated test engineering.

STATS' European customers can now have their test programs developed in Europe, and then seamlessly transferred into volume production at STATS' Singapore facility, according to Chee-Keong Tan, STATS vice president of worldwide strategic test development.

TDC services include generating test programs, converting existing programs to other test platforms and evaluating prototypes and first silicon devices [statsus.com].