Media Kit
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On Line Reader Service
 Publisher's Letter
300 mm Bumps and Grinds at 'Europa'

 Assembly Lines
UTAC's J.C. Lee Is 'The Man with the Plan' for the Singapore IC Assembler

 Opto-Electronically Speaking
Keep Those Cards & Letters Coming

 Electronic Trends
Chip Industry Growth to Return

 The View from Europe
European Fabless Companies Facing a Variety of IC Packaging Challenges

 The View from Asia
Hong Kong's Laissez Faire Approach Hastens Local IC Packaging's Demise

 Wafer-Level Watch
Wafer-Level Packaging Is Driving the Convergence of Fab and Assembly

 Packaging Insights
Look for Wafer-Level Packaging to Rule as the Natural Choice for Opto Packages

 Harvey Miller's Notebook
E-Waste Is the New Growth Industry!

 Industry News
Company News
Packaging Foundries
Opto/Nanotechnology
People in the News
Calendar of Events
Editorial Index

 Features
Special Feature: IC Package Design - Growing Chip Complexity Is Pushing the Envelope in CAD Design Tools
Special Feature: STATS Develops Design/Documentation Interface

IC Package Design Software Suites

Cover Story: Wafer Bumping - As the Technology Moves into the Mainstream, Some Technical Issues Remain

Cover Story: APiA - Advanced Packaging and Interconnect Alliance: Targeting Enhanced Productivity

Cover Story: SECAP - A Consortium to Address Equipment Integration Issues in Wafer-Level Packaging

International Directory of Wafer Bumping Service Providers

Cover Story: How Automated Visual Inspection and CD Metrology Will Impact Wafer-Level Packaging

Feature: Wafer-Level Packaging - Making 300mm a Reality

Emerging Technolgies: High-Resolution, Large-Area Projection Lithography Offers a New Alternative for Wafer-Level Packaging

Emerging Technolgies: A Lithography Cluster for Wafer-Level Packaging

 Tools & Technologies
K & S Introduces Bonder and more...

 Patents
Chip-Stacking Method Employs Standard Packaging Technology

 Archives
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Current Issue
The International Reference for Chip-Scale Electronics, Flip-Chip Technology, Optoelectronic Interconnection and Wafer-Level Packaging
July 2002

Calendar of Events

Please submit calendar listings to the editor at least two months prior to cover date. Due to limited space, listings are restricted to non-commercial, non-profit organizations.

July

15-16

PhoPack 2002
Photonic Devices & Systems Packaging, Stanford University, Palo Alto, Calif.
(Short courses presented on July 14.)
IEEE [cpmt.org/phopack]

17-19

SEMICON West
(Final Manufacturing)
17-18 10 a.m.-6 p.m.
19 10 a.m.-4 p.m.
San Jose Convention Center
SEMI [semi.org]

22-24

SEMICON West
(Wafer Processing)
22-23 10 a.m.-6 p.m.
24 10 a.m.-4 p.m.
Moscone Center, San Francisco
SEMI [semi.org]
August

22

International Wafer-Level Packaging Conference
8 a.m-5 p.m. Conference;
5-7 p.m. Reception and Tabletop Exhibits
Four Points Sheridan
1250 Lakeside Dr., Sunnyvale, Calif.
Presenter: Dr. Thomas H. Di Stefano, Decision Track Inc.
Sponsors: Chip Scale Review, MEPTEC, Microelectronics Forum
[mepteconline.com]

September

3-6

IMAPS 2002
3-6 Conference
4-6 Exhibition
Denver, Colorado Convention Center
IMAPS [imaps2002.org]

8-11

The 9th Annual International KGD Packaging and Test Workshop
"Die Products-Key to the Portable World"
Embassy Suites Napa Valley, Napa, Calif.
Die Products Consortium [dieproduct.com]

16-18

SEMICON Taiwan 2002
Taipei World Trade Center, Taipei
SEMI [semi.org]

22-26

SMTA International 2002
Donald Stevens Convention Center, Chicago
SMTA [smta.org]

24-28

SEMI Expo CIS 2002
New Manege Exhibition Hall
Moscow, Russia
SEMI [semi.org]
Alla Famitskaya [afamitskaya@semi.org]
October

3

Suppliers Expo
9 a.m.-6 p.m.
Santa Clara (Calif.) Convention Center
Fabless Semiconductor Association
[fsa.org]

15-16

SEMICON Southwest 2002
Austin (Texas) Convention Center
SEMI [semi.org]

 
Copyright © 2002