By Ron Iscoff, Editor
The increasing complexity of high-speed, high-performance ICs is pushing the envelope in package design CAD tools. Today, selecting the "right" IC package design software is a matter of both form and function-and therefore often difficult. Traditional linear design methods don't work very well with packages that offer thousands of pins, observes Joel McGrath, technical marketing manager at Cadence Design Systems, San Jose. For example, "Flip-chip designs approach 10,000 pins," he notes. This level of complexity demands that engineers understand and analyze the influence of the chip and its package on system performance early in the design cycle, says McGrath. Software now in development, he adds, will enable engineers to co-design the IC, the package and the board simultaneously, reducing development time by 20-60 percent-depending on design complexity. Dramatic Changes The package design software business has changed dramatically over the last 3-4 years. In the past, Xynetix was the dominant vendor. Today, a handful of suppliers compete for the business (see directory). Xynetix, meanwhile, was acquired by Avanti, which was recently acquired by Synopsys. PADS, which earlier sold to this market, merged with Innoveda in August 2000. Mentor Graphics of Wilsonville, Ore., completed a tender offer for Innoveda in May, at which time the future of PADS' package design software was uncertain. In addition, there are a significant number of software providers selling specialized "plug-ins" or stand-alone programs for parts of the layout design task, most notably electrical and thermal modeling. Software developers are rushing to keep up with escalating demands from users.
For example, Andres Carrasco, technical design manager at CAD Design Software, Los Gatos, Calif., notes that "routing has always been a problem since there have been no autorouters that handle radial designs effectively." Manual routing tools offer a poor substitute, he says. Additionally, the lack of support for custom fanouts (enhanced BGAs, MCMs and stacked packages) has created a bottleneck in the design process, Carrasco believes. He points out that no software has been able to offer signal integrity on the IC and the package at the same time. Kevin Rinebold, product marketing manager for Synopsys (formerly Avanti), Victor, N.Y., says that "an obvious challenge is keeping pace with rapidly evolving packaging technology," such as stacked die and high-density flip chip. Maintaining Functionality A not-so-obvious challenge, Rinebold adds, is maintaining functionality across the multiple domains that impact design. "Design tools must not only support substrates and assembly rules; they must also include functionality for electrical and thermal constraints. At the same time," he says, "they must maintain tight integration to adjacent levels of interconnection." Rinebold calls flip chip "a great example" of the need to design at both the silicon and package levels for optimal performance. Shrinking product sizes coupled with higher performance expectations are "placing unprecedented demands on the skills of package designers and the tools they use," says Les Ammann, director of AP technologies for software supplier Zuken USA, Westford, Mass. Most companies are forced to apply a number of CAD solutions to meet their packaging design needs, according to Bob Barilone, director of Amkor's Design Center in Chandler, Ariz.
"Some application choices are driven by design schedule goals, while others are dictated by package technology demands," says Barilone. Still other minor applications are employed as additional support for CAD tools that lack some needed functionality. "This," he adds, "is the package design world as we know it today." Only a few years ago, package design centered around leadframe packages and were primarily a mechanical design effort. "With the introduction of BGAs, all this began to change." While today's IC packaging includes both mechanical and electrical design considerations, the emphasis, says Barilone, is growing "exponentially" on the electrical side. Package design demands have progressed from a simple interposer to connect the silicon circuitry to the PC mother board to the creation of a design that is an electrically active part of the completed package. "Signal integrity factors such as controlled impedance, cross-talk, resistance and capacitance are playing an increasing role in how these connections are made. CAD systems, Barilone adds, "must recognize these factors, preferably in 3D form, and assist the designer" by incorporating them. Barilone says tomorrow's ideal package design tools will offer:
Edmund Law, director of design for ASAT in Fremont, Calif., says the Hong Kong-based company has been using one vendor's design suite for more complex IC packages such as BGAs, for many years. Law, meanwhile, continues to evaluate design software from other vendors. Law says the design suite ASAT currently employs "is very easy to use and very specific for IC packaging." Competitive software, he says, offers "a lot of features that evolved from PC board design, but are not needed for IC packaging." For less complex packages, QFPs for example, Law uses only AutoCAD software, since routing to traces is not required. ASAT employs separate programs for electrical and thermal modeling. Law says he can lay out a leaded package in 1-2 days, while a more complex format such as a BGA, may take 3-5 days. The "need for speed" in IC package design is nothing new. Perhaps, however, the demand for faster design cycle times has become more pressing as the optoelectronics market heats up. Market Windows Mario Aguirre of Fujitsu Microelectronics America, San Jose, says demands for shorter design cycles to meet aggressive market windows at reduced cost require "faster and faster" simulation tools. Reducing the design cycle has become particularly critical for optical network requirements, he adds The growth in few-chip packages, stacked packages and other multiple-component formats is also pushing the flexibility limits of package design tools. J.S. Kim, Signetics Korea, observes that package design software today must consider not only the single IC package solution, but the system solution-multiple ICs and other package components-as well. This is particularly needed, says Kim, with packaged RF devices. While almost all IC assembly is performed in Asia, most packaging foundries now offer extensive U.S.-based package design capability. Singapore's United Test and Assembly Center recently opened its first U.S. design center at UTAC America in Pleasanton, Calif. UTAC's design effort is headed by Dr. Anthony Sun, vice president of technology. Dr. Sun looks for improvements in wire bonding design functions. "Wire bonding has become more and more complicated," he observes, with in-line, staggered, tri-tier, stacked-die, reverse bond and other techniques. He looks for future design tools capable of checking 3D wires. Conclusion There is no perfect formula for the selection of IC package design software; nor is there a perfect design software suite, as users are often quick to proclaim. Certainly part of the tradeoff is in features. Selection often boils down to how many features you need and how many you want to pay for. There is always an aggressive group of software vendors with plug-ins and add-ons for many functions such as electrical and thermal modeling eager to bite off a chunk of the design business. |
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