Current Issue The International Reference for Chip-Scale Electronics, Flip-Chip Technology, Optoelectronic Interconnection and Wafer-Level Packaging July 2002 Email the editor

Infomation on products or services covered in this article

By Terrence E. Thompson, Editor-at-Large

Figure 1. This photograph of the wafer bumping process application was taken at the MicroFab factory in Singapore. (Ellipsiz)

Wafer-level bumping has become an increasingly important part of the wafer-level packaging (WLP) process, with a growing variety of bumping methods and numerous vendors that will bump your wafers-if you don't want to do it yourself.

There also are some interesting combinations of bump or stud types, as well as pad metallizations that vary between the low-volume niche and cost-driven, higher-volume uses. This article reviews these alternatives and discusses why some methods are more popular than others.

WLP: On a Roll

Why the boost for WLP? Why bumping in particular? Typically, WLP is a very economical approach for packaging and/or bumping CSP devices. Market analysts hotly contest the true volume of ICs bumped at the wafer level today. However, the consensus is that it's well under five percent of all chips. So, why all the interest in bumping wafers?

Bumping employs low-cost batch processing methods originally developed and used for front-end wafer fab and now adapted for WLP, Figures 1, 2. The bumped chips can easily be encapsulated, yielding a ready-to-use CSP at a relatively low cost.

Technology Tradeoffs

Every company in the IC packaging food chain intends to make money, but making the right choice requires doing some homework.

Most WLP technology process details are readily available. Major trade organizations (SEMI, SMTA, IPC) and technical societies (IMAPS, ECTC) offer a plethora of seminars on the technology. Recently formed groups such as WLP-oriented APiA and SECAP encourage potential users to investigate the technology (see sidebars).

Figure 2. Class 100 cleanroom used for wafer-bumping operations showing a lithography tool. (Ellipsiz)

Wafer-Level Bumping Needed

"Flip-chip (FC) packaging is attracting attention in the next-generation portable electronics equipment market because of its high-speed data processing capability," Figure 3, according to Masao Kuniba, of Gartner Dataquest [gartner.com].

"Solder bumping is the key technology in implementing flip-chip packaging, and wafer bumping service providers are doing well, even in the latest downturn of the semiconductor industry," the Gartner Dataquest analyst observes. In fact, according to information released by Kulicke & Soffa, its Flip Chip Division in Phoenix was the company's most profitable operation in FY2001.

Kuniba adds that current volume wafer bumping methods can be classified into the following five types:

1. Stud bumps formed by ball bonding using gold wire, Figure 4

2. Plated gold bumps using either electrolytic or electroless gold

3. Solder ball bumps with solder ball placement and reflow

4. Printed solder bumps using screen printing of solder paste by stencil

5. Plating solder bumping by electrolytic or electroless solder plating

Gold bumping methods 1 and 2 are primarily used for low-pin-count packages (40 pins/balls or fewer) Kuniba observes, such as chip-on-glass (COG), chip-on-flex (COF) and RF modules. Solder ball placement is not suitable for high-pin-count packages (300+ pins). This said, he still thinks most full-area FC packaging will be accomplished with solder bumps formed by printing or plating.

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