Common Categories When you specify bumps, there are some common categories that include solder (eutectic, low lead, low alpha particle) alloys, gold and copper. Additionally, lead-free is available for those who want to be environmentally friendly to end users. Finally, the selection may also include bump studs or column grid arrays-or the less common bumps, such as stenciled conductive polymers. Using special wire bonders, gold stud bumps can be formed, ready for subsequent coining or reflow operations if necessary, Figure 4. Some chip makers, and those buying fabricated wafers with completed devices on them, handle their own wafer bumping. The do-it-yourself drawback is obvious: You have up-front capital costs, need specialized process knowledge and must have a large enough volume to justify a bumping line, Figure 2. Technologies Make a Difference Is WLP the Holy Grail for almost all chips as some insist? The answer is "no." Despite widespread enthusiasm for WLP and WB, the number of discrete semiconductor devices has always outnumbered ICs and is likely to do so in the foreseeable future. APiA and SECAP? The Envelope, Please There are many issues in bumping and WLP worth noting, but we will only touch on a few of the more pertinent ones. First, does an end user, a capital equipment producer or a materials vendor need a consortium to further the goal of increased wafer-level packaging? If the answer is "yes," then we have two choices now. APiA and SECAP are, in fact, offering different ways to reach the same goal of using more WLP.
We also talked to bumping service providers for their take on where the markets and technologies are headed. We asked what the current bumping alternatives are, why some are more widely used than others and what requirements customers want in future products. Finding Acceptance Gil Olachea, president and CEO at K&S' Flip Chip Division noted, "The flip-chip market is increasingly finding comfortable acceptance by chip developers, designers, integrators and end users.
"The predominant obstacle to a wider market acceptance of flip chip is whether or not a completely developed infrastructure exists," Olachea added. "Key items such as substrates, test solutions, etc., are costly and underscore a move toward using less costly solutions for interconnect and packaging." Formation of the UBM and solder bump by using evaporation techniques was developed by IBM and is still widely used, Figure 5. However, sputtered UBM and solder paste bumping is today's dominant process and is used in K&S' FCT operation, Figure 6.
Customers Want 'Everything' For next generation packages, customers want "everything," according to C.J. Berry, director of advanced packaging wafer processes at Amkor Technology, Phoenix. When reviewing bumping options, said Berry, the requirements will usually dictate the bumping process. "Arguably, high-end, large die applications (ASIC, logic, networking, microprocessors, etc.) are where most of these bumping requirements converge. In this part of the applications space, customers are looking for 150 µm array pitches, better than 15 µm coplanarity, 99.5%+ die yields, electromigration-resistant structures, void-free solder bumps (primarily due to their influence on the former), and, eventually, lead-free solders," Berry added.
Leading Edge, Mature Processes Customers want leading-edge, mature processes (demonstrated CpK, thorough characterization and reliability data, etc.), and they want it-most likely-at an unrealistically low price. Less demanding applications present fewer important criteria, Berry noted. Power management applications need high current carrying capacity (electromigration resistance) at low cost, but die are smaller and pitch is about 250 µm, which eases yield concerns. Berry said another interesting bump opportunity is surfacing in the power amplifier arena: this is the 'front side' thermal management options provided by non-solder bump structures. Other next-generation processes getting airtime these days include flip-stacked applications involving pad-limiting metallization on substrate die, and multilevel redistribution for stacked wire bond applications. End Use What is important in a FC package and associated bump structure depends entirely what it will be used for.
Accept that any given company will have a finite process capability at its disposal at any point in time, or it will be predisposed to certain processing technologies. This said, the short answer to why some bump structures are more widely used than others is that they are selected based on achieving the best performance within the manufacturer's existing plant. "The simple truth is that people will use whatever is most easily available that provides the required quality. This is how the industry finds itself with the current process type make-up," Berry said.
Turnkey Providers Andrea Chen of Siliconware (SPIL Group), Tantzu, Taichung, Taiwan, said, "Customers for wafer bumping are looking for one-stop shopping; in other words, a turnkey provider. They want a supplier with a comprehensive list of services in addition to the wafer bumping process itself, covering wafer probe, package assembly and final test." She added that there is the growing expectation and need for a robust and reliable wafer bumping process that is cost-effective. Siliconware licensed such a technology from the K&S Flip Chip Division for its 200 mm wafer bumping process, given its long proven track record.
One Size Does Not Fit All Chen added that one bump process certainly does not fit all. SPIL has developed options to meet specific customers' needs, such as optional high-Pb, low-alpha and Pb-free solder bumps. To keep up with front-end development, SPIL now has a 300 mm wafer bumping process. Electroplating is one of the most widely used bumping technlogies according to Robert Lanzone, vice president of sales and marketing, Unitive Electronics Inc., Figure 7. Standard plating as shown in Figure 8 can achieve tight bump uniformity for very small pitches, he notes. Malaysia-based Carsem provides turnkey packaging and test services to the semiconductor industry. Paul Smith, Carsem's marketing director, said the company recently developed a strategic relationship with Ellipsiz-MicroFab in Singapore to form a wafer bumping partnership. This move will enable Carsem and MicroFab to provide customers with seamless flip-chip packaging solutions. Wafer bumping is an integral part of flip-chip technology, observed Smith, with FC an increasingly important advanced technology packaging solution for today's high-speed, mobile applications. Carsem earlier considered installing its own wafer bumping capability at Ipoh, Malaysia, said David Comley, Group Managing Director. They had seen bumped wafers from many sources over the past two years and were convinced that the industry and its technology were still evolving. This evolution sparked Carsem's choice of a third-party bumping provider, MicroFab. Some bump providers are very specialized to meet specific regional market demands said Gerald "Skip" Fehr, OSE USA. "We solely provide gold stud bumping here since that's what the customers want." |
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