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Cover Story: Wafer Bumping - As the Technology Moves into the Mainstream, Some Technical Issues Remain

Cover Story: APiA - Advanced Packaging and Interconnect Alliance: Targeting Enhanced Productivity

Cover Story: SECAP - A Consortium to Address Equipment Integration Issues in Wafer-Level Packaging

International Directory of Wafer Bumping Service Providers

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Feature: Wafer-Level Packaging - Making 300mm a Reality

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Current Issue
The International Reference for Chip-Scale Electronics, Flip-Chip Technology, Optoelectronic Interconnection and Wafer-Level Packaging
July 2002

SECAP: A Consortium to Address Equipment Integration Issues in Wafer-Level Packaging

Editor's Note: Chip Scale Review recently asked APiA and SECAP to contribute a one-page summary of their mission and activities.

The Semiconductor Equipment Consortium for Advanced Packaging (SECAP) was formed to address equipment integration issues between process steps for wafer-level packaging.

The Consortium is composed of the Fraunhofer Institute for Reliability and Microintegration [izm.thg.de/], Berlin, and noncompetitive process equipment companies. Fraunhofer is an open technical institute and therefore doesn't have competitive issues with SECAP.

Materials companies participate through open associate memberships enabling them to join in the marketing, technical presentations and conferences that SECAP offers.

Goals

SECAP's first goal was to coordinate a fab line that could run customer wafers for demo and R&D purposes. This line was established at Fraunhofer, and the Institute now uses SECAP member equipment.

Another goal was to produce a 300 mm wafer with an aggressive bumping pattern to prove the feasibility of WLP. This was accomplished in 2002 with 70 µm plated bumps, full mask patterns and full-face seed layers.

Ongoing research is another goal. With the rapid adoption of WLP, much of the development needs to be driven by SECAP.

Lead-free, thick-film resist, 3-D chips and low-cost processing techniques are all priorities for SECAP members and their customers.

A continuing goal is to bring other equipment manufactures that have complementary process steps into the SECAP consortium.

Overall, many of SECAP's activities are educational. With potential customers for SECAP equipment, we are making it clear that WLP is feasible and cost effective. Also, we provide education for SECAP members on integration issues that typically only device manufactures know (e.g., how do thin seed layers effect electroplating? How do lead-free chemistries wet the new photoresist materials?)

SECAP's Mission

The Consortium's mission is to support the advanced packaging industry by delivering optimized process equipment for wafer bumping, WLP and HDI technology. The membership is limited to equipment and material suppliers.

One recurring question presented to SECAP is, "Why doesn't SECAP align with potential customers?" The answer is that SECAP was chartered to provide technology to the entire packaging spectrum.

SECAP produced and displayed the first 300 mm high-density CSP wafer in the spring of 2000. All SECAP members are working with customers on joint development projects to characterize all the process steps for high-volume applications.

Projects by SECAP companies will move industry standards farther than any single company or an unstructured group of companies can accomplish. Likewise, ongoing joint R&D efforts at Fraunhofer, and individually with technology leaders, will address the specific issues that surface.

Since April 2001, SECAP has been able to run 300 mm wafers and it is continuing to streamline equipment sets and cost of ownership at different sites, including our current WLP line at Fraunhofer in Berlin.

The Consortium was officially organized in July 2000 at SEMICON West, when several equipment companies that had been working together met and formally organized under a charter.

Image Technology, Semitool, Suss MicroTec (Karl Suss), Unaxis (Balzers) and Fraunhofer were the founders.

In April 2002 at SEMICON Europa, SECAP teamed up with Infineon and ASE to address equipment options for next-generation devices then under development. This June, the first all WLP seminar in North America was held in Montana.

The focus was 3-D IC processing, advanced photolithography for thick film and electro-phoretic resist applications, and lead-free processing from UBM to electroplating interconnects.

At SEMICON West this year, SECAP will host a large WLP tutorial in conjunction with the show. The focus will be on fab integration, and will be targeted at the front-end decision makers, since cost drivers and technical challenges are increasingly being felt in the front end.

 
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