By Dr. Christian Linder, Wolfgang Rietzler and Hans Auer, Unaxis Semiconductors, Balzers, Liechtenstein
Despite the semiconductor industry's recent downturn (or perhaps because of it), the transition to 300-mm wafer processing has gained momentum. Several independent device makers (IDMs) worldwide are operating initial 300-mm wafer production lines. Many more have concrete plans to establish 300-mm processing in the near future. Among the key drivers for 300-mm technology are cost reduction, higher production volume, increased silicon utilization, high-level automation and enhanced reliability. These advantages are needed to prepare for the anticipated upswing and to satisfy future cost and volume needs. Production Lines At the moment, between 15-20 production lines are running, and more are scheduled to begin this year and next. Since the 300-mm fabs are focused on front-end device production, tremendous pressure has been imposed on the packaging companies to adopt 300-mm wafer-level packaging. Initial 300-mm devices were packaged conventionally, (e. g., wire bonded). WLP and wafer bumping now completely change the picture, however. IDMs, mainly in the field of high performance device production like microprocessors, were the first to implement WLP for 300 mm, to achieve increased silicon area use. Typically, however, the IDM's production capacity is captive and not accessible to those who would like to have 300-mm wafers bumped. About a year ago, a few packaging foundries in Taiwan decided to implement 300-mm WLP lines. Additional lines in Taiwan, as well as Singapore and possibly Korea, are currently in the planning stages. Besides the packaging and bumping foundries, IDMs focusing on DRAMs and other high-volume devices have begun to establish 300-mm WLP. For DRAMs, the lower cost of 300-mm production, as well as the advantage of a wafer-level package are the key drivers. While WLP using bumping and redistribution technology is recognized as an important concept in advanced packaging, it currently represents only two percent of total device production, with a predicted growth rate of 35 to 40% over the next five years.
To date, WLP has mainly been used for high I/O (microprocessor, high-end logic), high-frequency devices and LC driver ICs. Promising future applications include higher-volume devices, such as DRAMs, SRAMs, ASICs, and passives. Lower Cost, Enabling Technology With the move to 300 mm, WLP becomes even more attractive as the solution for backend processing, initially because of lower cost, but more importantly as an enabling technology for the most advanced 0.13 micron technology using Cu/low-k interconnect devices. Cu/low-k devices need WLP since wire-bond forces could damage the soft device structures. Additionally, low-k interconnect densities often reach values that can only be accommodated by area-array packaging technology. The major bumping process steps include underbump metallization (UBM) or redistribution (RDL) using physical-vapor deposition (PVD), photolithography, electroplating, stencil printing, metal wet etching, resist stripping, and reflowing bumps.
Sputtering Processes By employing the PVD, UBM and RDL, sputtering processes for advanced packaging have been successfully performed for many years in 150-mm as well as 200-mm production at leading WLP companies (See Figures 1 and 2). Significant benefits of an existing leading-edge sputtering system should include:
UBM/RDL Applications In UBM and RDL applications, a typical sequence begins with a clean-etch step using an ICP source, which induces no damage to the fabricated dies on the wafer. This etching step removes native oxides and other materials, such as organic residues, from the wafer surface. The subsequent metal film deposition (first metal of the UBM/RDL stack, e.g., Ti or Al) achieve a low contact resistivity to the metal pads of the dies and optimum adhesion to the pads, as well as to the passivation layers on the wafer surface. Next, barrier metal films such as NiV, TiW (or other materials) are deposited to prevent diffusion of the bump metals into the die metals. The top metals of the UBM stack are used as seed layers, for subsequent plating (Cu, NiV, or Au), or as wettable material for the solder of printed bumps. In RDL, the top metals serve as the conductive interconnect lines (Al, Cu, for example). Electrical film properties can be selected for the lowest possible resistivity at a given maximum process temperature, and for appropriate uniformity. This "tuning" enables precise metal wet etching or homogeneously distributed plating current for uniform bump heights. Furthermore, depending on the film material, the mechanical stress can be specifically controlled by means of process power, gas flow, temperature or RF bias. The results are low-stress film stacks providing mechanical stability-needed for the long-term reliability of the bump structure. Close partnerships with leading IDMs and experienced equipment manufacturers play an essential part in the successful operation of any sophisticated production machine. Currently, the Unaxis CLUSTERLINE 300 is being employed in the first 300-mm wafer bumping fab at one of the world's largest providers of IC packaging and testing services. Summary The transition to 300-mm wafer processing is gaining momentum. The 300-mm wafer fabs are placing tremendous pressure on the backend to adopt WLP. Although now only accounting for about 2 percent of packaged devices, experts are forecasting a growth rate of 35-40 percent annually. Sputtering has proven itself to be a reliable method of depositing UBM and RDL.
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