PATENT NUMBER: 6,339,254 ASSIGNEE: Texas Instruments INVENTORS: Vaiyapuri Venkateshwaran and Ji Cheng Yang TITLE: Stacked Flip-Chip Integrated Circuit Assemblage As the title indicates, this patent describes a stacked flip-chip package that is also a CSP. One example of prior art shows a flip-chip device mounted in a BGA-style package. The present example shows that solder ball mounting methods have expanded to employ a much larger range of ball diameters. A second example of prior art shows two chips bonded face-to-face across a TAB frame that is bonded to a substrate. This approach is a more complex assembly method and is best suited for chips that are similar in size. The Invention The goal of this patent is to provide a method of stacking chips that can use standard packaging technology and which take full advantage of a low inductance flip-chip mounting method. As shown in the figure, the approach is a very simple one: Both die are flip-chip bonded to the same substrate. One die has its contacts arranged in an area-array format, while the second and larger die employs a perimeter arrangement for its bonding pads. An advantage of the perimeter-arrangement approach is that both die are connected to the same substrate surface. It is apparent from the figure that different size solder bumps are required for the different devices, with the larger bumps used on the top device. The bump size on the bottom (or smaller die) is between 0.05 and 0.25 mm (2-10 mils) in diameter. Because the top die is larger, larger size bumps are required-not only to clear the lower die, but to be able to handle the greater thermal stresses. The solder balls used on the top die possess a diameter of 0.25 to 0.6 mm (10-24 mils).
A suitable underfill is applied to both die. The underfill includes thermally conductive particles to assist in heat removal and to control expansion. The back surface of the top die can be exposed for attaching a heat sink. Additional thermal dissipation occurs through the solder bumps down to the substrate and board. The larger bumps on the top die create a standoff space between it and the bottom die. If the maximum diameter of the top solder balls is 0.35 mm (14 mils), the thickness of the bottom die must be less than 0.2 mm (10 mils). Die for thinned packages are currently thinned to 0.15 mm (6 mils).
In addition to underfilling the flip-chip solder joints, the package can be further protected by transfer molding or a cap can be applied. The solder used for the flip-chip bumps should have a higher melting temperature than the eutectic solder used for mounting the package. Summary This packaging method is suitable for mounting two dissimilar die in a CSP using standard assembly methods.
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